From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org
Cc: namhyung@kernel.org, eranian@google.com, irogers@google.com,
gmx@google.com, acme@kernel.org, jolsa@redhat.com,
ak@linux.intel.com, benh@kernel.crashing.org, paulus@samba.org,
mpe@ellerman.id.au, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 2/3] perf/x86/intel: Set PERF_ATTACH_SCHED_CB for large PEBS and LBR
Date: Mon, 30 Nov 2020 11:38:41 -0800 [thread overview]
Message-ID: <20201130193842.10569-2-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20201130193842.10569-1-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
To supply a PID/TID for large PEBS, it requires flushing the PEBS buffer
in a context switch.
For normal LBRs, a context switch can flip the address space and LBR
entries are not tagged with an identifier, we need to wipe the LBR, even
for per-cpu events.
For LBR callstack, save/restore the stack is required during a context
switch.
Set PERF_ATTACH_SCHED_CB for the event with large PEBS & LBR.
Fixes: 9c964efa4330 ("perf/x86/intel: Drain the PEBS buffer during context switches")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
Changes since V1
- Set PERF_ATTACH_SCHED_CB for a LBR event as well
arch/x86/events/intel/core.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index f1926e9f2143..534e0c84f7f8 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3564,8 +3564,10 @@ static int intel_pmu_hw_config(struct perf_event *event)
if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
if (!(event->attr.sample_type &
- ~intel_pmu_large_pebs_flags(event)))
+ ~intel_pmu_large_pebs_flags(event))) {
event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
+ event->attach_state |= PERF_ATTACH_SCHED_CB;
+ }
}
if (x86_pmu.pebs_aliases)
x86_pmu.pebs_aliases(event);
@@ -3578,6 +3580,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
ret = intel_pmu_setup_lbr_filter(event);
if (ret)
return ret;
+ event->attach_state |= PERF_ATTACH_SCHED_CB;
/*
* BTS is set up earlier in this path, so don't account twice
--
2.17.1
next prev parent reply other threads:[~2020-11-30 19:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-30 19:38 [PATCH V2 1/3] perf/core: Flush PMU internal buffers for per-CPU events kan.liang
2020-11-30 19:38 ` kan.liang [this message]
2021-03-01 10:16 ` [tip: perf/urgent] perf/x86/intel: Set PERF_ATTACH_SCHED_CB for large PEBS and LBR tip-bot2 for Kan Liang
2021-03-06 11:54 ` tip-bot2 for Kan Liang
2020-11-30 19:38 ` [PATCH V2 3/3] perf: Optimize sched_task() in a context switch kan.liang
2020-12-01 17:29 ` Peter Zijlstra
2020-12-02 10:26 ` Peter Zijlstra
2020-12-02 14:40 ` Namhyung Kim
2020-12-04 7:14 ` Namhyung Kim
2020-12-10 7:13 ` Namhyung Kim
2020-12-10 13:52 ` Liang, Kan
2020-12-10 14:25 ` Peter Zijlstra
2021-01-18 7:04 ` Namhyung Kim
2021-01-27 4:41 ` Namhyung Kim
2021-02-22 9:46 ` Namhyung Kim
2020-12-01 17:21 ` [PATCH V2 1/3] perf/core: Flush PMU internal buffers for per-CPU events Peter Zijlstra
2021-03-01 10:16 ` [tip: perf/urgent] " tip-bot2 for Kan Liang
2021-03-06 11:54 ` tip-bot2 for Kan Liang
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