From: Vinod Koul <vkoul@kernel.org>
To: Taniya Das <tdas@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Vivek Aknurwar <viveka@codeaurora.org>,
Andy Gross <agross@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jeevan Shriram <jshriram@codeaurora.org>
Subject: Re: [PATCH 5/5] clk: qcom: gcc: Add clock driver for SM8350
Date: Fri, 4 Dec 2020 15:49:14 +0530 [thread overview]
Message-ID: <20201204101914.GO8403@vkoul-mobl> (raw)
In-Reply-To: <302cf18a-080d-a521-8c7a-39c265fbceb8@codeaurora.org>
Hi Taniya,
On 04-12-20, 14:20, Taniya Das wrote:
> On 12/4/2020 10:05 AM, Vinod Koul wrote:
> > On 03-12-20, 18:06, Bjorn Andersson wrote:
> > > On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
> > > > diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
> > > [..]
> > > > +static int gcc_sm8350_probe(struct platform_device *pdev)
> > > > +{
> > > > + struct regmap *regmap;
> > > > + int ret;
> > > > +
> > > > + regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
> > > > + if (IS_ERR(regmap)) {
> > > > + dev_err(&pdev->dev, "Failed to map gcc registers\n");
> > > > + return PTR_ERR(regmap);
> > > > + }
> > > > +
> > > > + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> > > > + regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
> > > > +
> > > > + /*
> > > > + * Enable clocks required by the i2c-connected pm8008 regulators. Don't
> > > > + * register them with the clock framework so that client requests are
> > > > + * short-circuited before grabbing the enable/prepare locks. This
> > > > + * prevents deadlocks between the clk/regulator frameworks.
> > > > + *
> > > > + * gcc_qupv3_wrap_1_m_ahb_clk
> > > > + * gcc_qupv3_wrap_1_s_ahb_clk
> > > > + * gcc_qupv3_wrap1_s5_clk
> > > > + */
> > >
> > > Isn't this a workaround inherited from the downstream control of
> > > regulators from within the clock core? Does this still apply upstream?
> >
> > Let me check on this bit...
> >
> > Thanks
> >
>
> No it should not apply.
Thanks for confirmation, removed now. Will send v2
--
~Vinod
prev parent reply other threads:[~2020-12-04 10:20 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-03 7:02 [PATCH 0/5] Add clock drivers for SM8350 Vinod Koul
2020-12-03 7:02 ` [PATCH 1/5] dt-bindings: clock: Add RPMHCC bindings " Vinod Koul
2020-12-03 23:56 ` Bjorn Andersson
2020-12-03 7:02 ` [PATCH 2/5] clk: qcom: rpmh: add support for SM8350 rpmh clocks Vinod Koul
2020-12-03 23:55 ` Bjorn Andersson
2020-12-03 7:02 ` [PATCH 3/5] dt-bindings: clock: Add SM8350 GCC clock bindings Vinod Koul
2020-12-03 7:02 ` [PATCH 4/5] clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL Vinod Koul
2020-12-03 7:02 ` [PATCH 5/5] clk: qcom: gcc: Add clock driver for SM8350 Vinod Koul
2020-12-04 0:06 ` Bjorn Andersson
2020-12-04 4:35 ` Vinod Koul
2020-12-04 8:50 ` Taniya Das
2020-12-04 10:19 ` Vinod Koul [this message]
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