From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3BD3C433FE for ; Wed, 9 Dec 2020 23:41:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3B8682343F for ; Wed, 9 Dec 2020 23:41:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388755AbgLIXlN (ORCPT ); Wed, 9 Dec 2020 18:41:13 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:47518 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727028AbgLIXlN (ORCPT ); Wed, 9 Dec 2020 18:41:13 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kn94G-00B8S3-JC; Thu, 10 Dec 2020 00:40:20 +0100 Date: Thu, 10 Dec 2020 00:40:20 +0100 From: Andrew Lunn To: Pavana Sharma Cc: ashkan.boldaji@digi.com, clang-built-linux@googlegroups.com, davem@davemloft.net, devicetree@vger.kernel.org, f.fainelli@gmail.com, gregkh@linuxfoundation.org, kbuild-all@lists.01.org, kuba@kernel.org, linux-kernel@vger.kernel.org, lkp@intel.com, marek.behun@nic.cz, netdev@vger.kernel.org, robh+dt@kernel.org, vivien.didelot@gmail.com Subject: Re: [PATCH v11 4/4] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell Message-ID: <20201209234020.GI2649111@lunn.ch> References: <9db13ff47826f8bf9d08ec7cdc194c2187868a40.1607488953.git.pavana.sharma@digi.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9db13ff47826f8bf9d08ec7cdc194c2187868a40.1607488953.git.pavana.sharma@digi.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > +/* Support 10, 100, 200, 1000, 2500, 5000, 10000 Mbps (e.g. 88E6393X) > + * This function adds new speed 5000 supported by Amethyst family. > + * Function mv88e6xxx_port_set_speed_duplex() can't be used as the register > + * values for speeds 2500 & 5000 conflict. > + */ Thanks, that should stop my or somebody else trying to wrong combine them. > +/* Offset 0x10 & 0x11: EPC */ > + > +static int mv88e6393x_epc_wait_ready(struct mv88e6xxx_chip *chip, int port) > +{ > + int bit = __bf_shf(MV88E6393X_PORT_EPC_CMD_BUSY); > + > + return mv88e6xxx_port_wait_bit(chip, port, MV88E6393X_PORT_EPC_CMD, bit, 0); > +} To follow the naming convention, this should really be called mv88e6393x_port_epc_wait_ready > +int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, > + int lane, bool enable) It can be hard to tell in a diff, but the indentation looks wrong here. 'int lane' should line up with 'struct'. > +{ > + u8 cmode = chip->ports[port].cmode; > + int err = 0; > + > + switch (cmode) { > + case MV88E6XXX_PORT_STS_CMODE_SGMII: > + case MV88E6XXX_PORT_STS_CMODE_1000BASEX: > + case MV88E6XXX_PORT_STS_CMODE_2500BASEX: > + case MV88E6XXX_PORT_STS_CMODE_5GBASER: > + case MV88E6XXX_PORT_STS_CMODE_10GBASER: > + err = mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable); > + } > + > + return err; > +} > + > +irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, > + int lane) Maybe here as well? > +int mv88e6393x_setup_errata(struct mv88e6xxx_chip *chip) It should have _serdes_ in the name to follow the naming convention. Andrew