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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id j73sm837962otj.37.2020.12.09.19.49.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Dec 2020 19:49:48 -0800 (PST) Received: (nullmailer pid 1624587 invoked by uid 1000); Thu, 10 Dec 2020 03:49:47 -0000 Date: Wed, 9 Dec 2020 21:49:47 -0600 From: Rob Herring To: Kevin Tang Cc: maarten.lankhorst@linux.intel.com, mripard@kernel.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, mark.rutland@arm.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v1 3/6] dt-bindings: display: add Unisoc's dpu bindings Message-ID: <20201210034947.GA1622093@robh.at.kernel.org> References: <1607352626-26088-1-git-send-email-kevin3.tang@gmail.com> <1607352626-26088-4-git-send-email-kevin3.tang@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1607352626-26088-4-git-send-email-kevin3.tang@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 07, 2020 at 10:50:23PM +0800, Kevin Tang wrote: > From: Kevin Tang > > DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs > which transfers the image data from a video memory buffer to an internal > LCD interface. > > Cc: Orson Zhai > Cc: Chunyan Zhang > Signed-off-by: Kevin Tang > --- > .../bindings/display/sprd/sprd,sharkl3-dpu.yaml | 83 ++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml > > diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml > new file mode 100644 > index 0000000..a9052e1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Unisoc Sharkl3 Display Processor Unit (DPU) > + > +maintainers: > + - Kevin Tang > + > +description: | > + DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs > + which transfers the image data from a video memory buffer to an internal > + LCD interface. > + > +properties: > + compatible: > + const: sprd,sharkl3-dpu > + > + reg: > + maxItems: 1 > + description: > + Physical base address and length of the DPU registers set Drop. Nothing unique about this. > + > + interrupts: > + maxItems: 1 > + description: > + The interrupt signal from DPU Drop. > + > + clocks: > + minItems: 2 > + > + clock-names: > + items: > + - const: clk_src_128m > + - const: clk_src_384m > + > + power-domains: > + maxItems: 1 > + description: A phandle to DPU power domain node. Drop. > + > + iommus: > + maxItems: 1 > + description: A phandle to DPU iommu node. Drop. With those, Reviewed-by: Rob Herring > + > + port: > + type: object > + description: > + A port node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + That port should be the output endpoint, usually output to > + the associated DSI. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - port > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + dpu: dpu@63000000 { > + compatible = "sprd,sharkl3-dpu"; > + reg = <0x63000000 0x1000>; > + interrupts = ; > + clock-names = "clk_src_128m", "clk_src_384m"; > + > + clocks = <&pll CLK_TWPLL_128M>, > + <&pll CLK_TWPLL_384M>; > + > + dpu_port: port { > + dpu_out: endpoint { > + remote-endpoint = <&dsi_in>; > + }; > + }; > + }; > -- > 2.7.4 >