From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8F3AC433FE for ; Fri, 11 Dec 2020 09:08:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 817B923F36 for ; Fri, 11 Dec 2020 09:08:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437362AbgLKJHs (ORCPT ); Fri, 11 Dec 2020 04:07:48 -0500 Received: from esa.microchip.iphmx.com ([68.232.154.123]:56596 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2437344AbgLKJHQ (ORCPT ); Fri, 11 Dec 2020 04:07:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1607677635; x=1639213635; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7zj8OkiqVP0y2v8pLf60YgrsvbAJ9ccfq8Fe3AUJvYA=; b=QJ1/mG6uA1smkvZRVRRFQ3ZKSGB+2+0Lz1q09AkLSqBjhWFBXZpoMSL4 24v6nz0elxRMJSydbbtVEmmhDNc1D7gs1Xl4BZqCpDGLnLX2NYtYbfZVa OenRh7DCOMOy/QnS7Q4KaizXqLwDfTHgpScvzIP5etqHhZMdN0XQDBFFK 93MPEFHaynmrrLLi873GExsKSpp2Pj/UVbB6lOdAdWLTJLBFYKCGX7SmV 8I9l3RbSGg/YNirPnBzn726/tjbzwZmt782vCyDSFBC5tdFy3dRlsRyni F1h0LMaI+7QY7UujQMOLSR/dWogRWDea9lwQrhY8j6HgSJNC5Wp3V9QXP Q==; IronPort-SDR: XTycn5HdSqoQJjgWgu+D9hxmHW65vG+QpzTDZkR90p5/DmSYTTFlxIzrfNgHDAINnpl+n3zxm5 HepqwWp/9HELpb6cmYsEYW6yl/d7P192x5qzu/9zQYjQxEWtLAX7vRNSFWPjyAc2a34ZdX0Dep V3u9g6DDM86QxgqCih+aEDLLFyYShoVuNogpNLVwFSB3iAlIjWqz94Tr1PmP9qQ3dKu30bmIfq etEzDckBBqwf+8dyLFxdvSNbWgyreM/W5Cl9YKN0sPzLAYGYcD3tNt8FyWC4vJe2QXGkQ+9WWy 5Sw= X-IronPort-AV: E=Sophos;i="5.78,410,1599548400"; d="scan'208";a="99484063" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 11 Dec 2020 02:06:00 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 11 Dec 2020 02:05:59 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 11 Dec 2020 02:05:57 -0700 From: Steen Hegelund To: Kishon Vijay Abraham I , Vinod Koul CC: Steen Hegelund , Alexandre Belloni , Lars Povlsen , Bjarni Jonasson , Microchip UNG Driver List , , Subject: [PATCH v10 2/4] phy: Add ethernet serdes configuration option Date: Fri, 11 Dec 2020 10:05:39 +0100 Message-ID: <20201211090541.157926-3-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201211090541.157926-1-steen.hegelund@microchip.com> References: <20201211090541.157926-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Provide a new ethernet phy configuration structure, that allow PHYs used for ethernet to be configured with speed, media type and clock information. Signed-off-by: Lars Povlsen Signed-off-by: Steen Hegelund --- include/linux/phy/phy-ethernet-serdes.h | 30 +++++++++++++++++++++++++ include/linux/phy/phy.h | 4 ++++ 2 files changed, 34 insertions(+) create mode 100644 include/linux/phy/phy-ethernet-serdes.h diff --git a/include/linux/phy/phy-ethernet-serdes.h b/include/linux/phy/phy-ethernet-serdes.h new file mode 100644 index 000000000000..d2462fadf179 --- /dev/null +++ b/include/linux/phy/phy-ethernet-serdes.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Microchip Sparx5 Ethernet SerDes driver + * + * Copyright (c) 2020 Microschip Inc + */ +#ifndef __PHY_ETHERNET_SERDES_H_ +#define __PHY_ETHERNET_SERDES_H_ + +#include + +enum ethernet_media_type { + ETH_MEDIA_DEFAULT, + ETH_MEDIA_SR, + ETH_MEDIA_DAC, +}; + +/** + * struct phy_configure_opts_eth_serdes - Ethernet SerDes This structure is used + * to represent the configuration state of a Ethernet Serdes PHY. + * @speed: Speed of the serdes interface in Mbps + * @media_type: Specifies which media the serdes will be using + */ +struct phy_configure_opts_eth_serdes { + u32 speed; + enum ethernet_media_type media_type; +}; + +#endif + diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index e435bdb0bab3..78ecb375cede 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -18,6 +18,7 @@ #include #include +#include struct phy; @@ -49,11 +50,14 @@ enum phy_mode { * * @mipi_dphy: Configuration set applicable for phys supporting * the MIPI_DPHY phy mode. + * @eth_serdes: Configuration set applicable for phys supporting + * the ethernet serdes. * @dp: Configuration set applicable for phys supporting * the DisplayPort protocol. */ union phy_configure_opts { struct phy_configure_opts_mipi_dphy mipi_dphy; + struct phy_configure_opts_eth_serdes eth_serdes; struct phy_configure_opts_dp dp; }; -- 2.29.2