From: Mark Brown <broonie@kernel.org>
To: Sowjanya Komatineni <skomatineni@nvidia.com>
Cc: thierry.reding@gmail.com, jonathanh@nvidia.com,
robh+dt@kernel.org, lukas@wunner.de, linux-spi@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Boris Brezillon <bbrezillon@kernel.org>,
Pratyush Yadav <p.yadav@ti.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: Re: [PATCH v2 5/9] spi: spi-mem: Allow masters to transfer dummy cycles directly by hardware
Date: Fri, 11 Dec 2020 18:33:20 +0000 [thread overview]
Message-ID: <20201211183320.GH4929@sirena.org.uk> (raw)
In-Reply-To: <1607706088-1437-8-git-send-email-skomatineni@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 2894 bytes --]
On Fri, Dec 11, 2020 at 09:01:24AM -0800, Sowjanya Komatineni wrote:
> This patch adds a flag SPI_MASTER_USES_HW_DUMMY_CYCLES for the controllers
> that support transfer of dummy cycles by the hardware directly.
>
> For controller with this flag set, spi-mem driver will skip dummy bytes
> transfer in the spi message.
>
> Controller drivers can get the number of dummy cycles from spi_message.
Copying more people who've worked on spi-mem for their review - I've not
got such a good perspective on controller features.
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/spi/spi-mem.c | 18 +++++++++++-------
> include/linux/spi/spi.h | 8 ++++++++
> 2 files changed, 19 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
> index f3a3f19..38a523b 100644
> --- a/drivers/spi/spi-mem.c
> +++ b/drivers/spi/spi-mem.c
> @@ -350,13 +350,17 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> }
>
> if (op->dummy.nbytes) {
> - memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes);
> - xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
> - xfers[xferpos].len = op->dummy.nbytes;
> - xfers[xferpos].tx_nbits = op->dummy.buswidth;
> - spi_message_add_tail(&xfers[xferpos], &msg);
> - xferpos++;
> - totalxferlen += op->dummy.nbytes;
> + if (ctlr->flags & SPI_MASTER_USES_HW_DUMMY_CYCLES) {
> + msg.dummy_cycles = (op->dummy.nbytes * 8) / op->dummy.buswidth;
> + } else {
> + memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes);
> + xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
> + xfers[xferpos].len = op->dummy.nbytes;
> + xfers[xferpos].tx_nbits = op->dummy.buswidth;
> + spi_message_add_tail(&xfers[xferpos], &msg);
> + xferpos++;
> + totalxferlen += op->dummy.nbytes;
> + }
> }
>
> if (op->data.nbytes) {
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index aa09fdc..2024149 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -512,6 +512,8 @@ struct spi_controller {
>
> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
>
> +#define SPI_MASTER_USES_HW_DUMMY_CYCLES BIT(6) /* HW dummy bytes transfer */
> +
> /* flag indicating this is an SPI slave controller */
> bool slave;
>
> @@ -1022,6 +1024,12 @@ struct spi_message {
> unsigned actual_length;
> int status;
>
> + /*
> + * dummy cycles in the message transfer. This is used by the controller
> + * drivers supports transfer of dummy cycles directly by the hardware.
> + */
> + u8 dummy_cycles;
> +
> /* for optional use by whatever driver currently owns the
> * spi_message ... between calls to spi_async and then later
> * complete(), that's the spi_controller controller driver.
> --
> 2.7.4
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
next prev parent reply other threads:[~2020-12-11 20:06 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-11 17:01 [PATCH v2 0/9] Add Tegra Quad SPI driver Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 1/9] dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 2/9] dt-bindings: spi: Add Tegra QSPI device tree binding Sowjanya Komatineni
2020-12-11 20:55 ` Rob Herring
2020-12-11 17:01 ` [PATCH v2 2/9] dt-bindings: spi: Add Tegra Quad SPI " Sowjanya Komatineni
2020-12-11 20:56 ` Rob Herring
2020-12-11 21:07 ` Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 3/9] MAINTAINERS: Add Tegra QSPI driver section Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 3/9] MAINTAINERS: Add Tegra Quad SPI " Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 4/9] spi: tegra210-quad: Add support for Tegra210 QSPI controller Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 5/9] spi: spi-mem: Allow masters to transfer dummy cycles directly by hardware Sowjanya Komatineni
2020-12-11 18:33 ` Mark Brown [this message]
2020-12-11 21:06 ` Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 6/9] spi: tegra210-quad: Add support for hardware dummy cycles Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 7/9] arm64: tegra: Enable QSPI on Jetson Nano Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 8/9] arm64: tegra: Add QSPI nodes on Tegra194 Sowjanya Komatineni
2020-12-11 17:01 ` [PATCH v2 9/9] arm64: tegra: Enable QSPI on Jetson Xavier NX Sowjanya Komatineni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201211183320.GH4929@sirena.org.uk \
--to=broonie@kernel.org \
--cc=bbrezillon@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jonathanh@nvidia.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=lukas@wunner.de \
--cc=p.yadav@ti.com \
--cc=robh+dt@kernel.org \
--cc=skomatineni@nvidia.com \
--cc=thierry.reding@gmail.com \
--cc=tudor.ambarus@microchip.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).