* [RFC PATCH 00/12] Support for Allwinner V831 SoC
@ 2020-12-12 4:01 Icenowy Zheng
2020-12-12 4:01 ` [RFC PATCH 01/12] dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU Icenowy Zheng
` (11 more replies)
0 siblings, 12 replies; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:01 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng
Allwinner V831 is a new SoC by Allwinner oriented at the camera market.
It has a QFN88 package with co-packaged 64MiB DDR2 DRAM. Another SoC,
V833, is also available, which has the same die with V831 but w/o
co-packaged DRAM (thus a BGA package).
This patchset tries to add basical support for V831, with consideration
of V833 in many drivers.
The DT is only for a temporary test device w/o schematics, development
will be shifted to another device when the patchset leaves RFC.
Icenowy Zheng (12):
dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU
dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers
clk: sunxi-ng: add CCU driver for V831/V833
dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl
pinctrl: sunxi: add pinctrl driver for V831/V833
dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC
rtc: sun6i: add compatible string for V831/V833 RTC
dt-bindings: mmc: sunxi: add compatible strings for V831 MMC
dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT
dt-bindings: spi: sun6i: add compatible for V831 SPI
ARM: dts: sun8i: add DTSI file for V831
[DO NOT MERGE] ARM: dts: sun8i: v831: add a device tree file for Y20GA
.../clock/allwinner,sun4i-a10-ccu.yaml | 2 +
.../bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 3 +
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 4 +
.../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 2 +
.../bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
.../watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts | 53 +
arch/arm/boot/dts/sun8i-v831.dtsi | 244 +++++
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-v833.c | 930 ++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-v833.h | 46 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c | 743 ++++++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
drivers/rtc/rtc-sun6i.c | 18 +
include/dt-bindings/clock/sun8i-v833-ccu.h | 89 ++
include/dt-bindings/reset/sun8i-v833-ccu.h | 52 +
20 files changed, 2206 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
create mode 100644 arch/arm/boot/dts/sun8i-v831.dtsi
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v833.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v833.h
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
create mode 100644 include/dt-bindings/clock/sun8i-v833-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-v833-ccu.h
--
2.28.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* [RFC PATCH 01/12] dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
@ 2020-12-12 4:01 ` Icenowy Zheng
2020-12-15 16:16 ` Rob Herring
2020-12-12 4:03 ` [RFC PATCH 02/12] dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers Icenowy Zheng
` (10 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:01 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng
V831/V833 has a CCU similar to the ones on H6/A100.
Add a compatible string for it.
As the user manual do not mention the difference between V831 and V833
in the CCU chapter, only a single compatible string for V833
(full-functional chip) is made.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
index 3b45344ed758..b874d887995a 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -33,6 +33,7 @@ properties:
- allwinner,sun8i-r40-ccu
- allwinner,sun8i-v3-ccu
- allwinner,sun8i-v3s-ccu
+ - allwinner,sun8i-v833-ccu
- allwinner,sun9i-a80-ccu
- allwinner,sun50i-a64-ccu
- allwinner,sun50i-a64-r-ccu
@@ -98,6 +99,7 @@ else:
properties:
compatible:
enum:
+ - allwinner,sun8i-v833-ccu
- allwinner,sun50i-a100-ccu
- allwinner,sun50i-h6-ccu
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 02/12] dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
2020-12-12 4:01 ` [RFC PATCH 01/12] dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU Icenowy Zheng
@ 2020-12-12 4:03 ` Icenowy Zheng
2020-12-15 16:18 ` Rob Herring
2020-12-12 4:03 ` [RFC PATCH 03/12] clk: sunxi-ng: add CCU driver for V831/V833 Icenowy Zheng
` (9 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:03 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng
As the device tree needs the clock/reset indices, add them to DT binding
headers.
The driver itself will be then added.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
include/dt-bindings/clock/sun8i-v833-ccu.h | 89 ++++++++++++++++++++++
include/dt-bindings/reset/sun8i-v833-ccu.h | 52 +++++++++++++
2 files changed, 141 insertions(+)
create mode 100644 include/dt-bindings/clock/sun8i-v833-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-v833-ccu.h
diff --git a/include/dt-bindings/clock/sun8i-v833-ccu.h b/include/dt-bindings/clock/sun8i-v833-ccu.h
new file mode 100644
index 000000000000..885f3462eab6
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-v833-ccu.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2020 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_V833_H_
+#define _DT_BINDINGS_CLK_SUN8I_V833_H_
+
+#define CLK_CPUX 14
+
+#define CLK_APB1 19
+
+#define CLK_DE 21
+#define CLK_BUS_DE 22
+#define CLK_G2D 23
+#define CLK_BUS_G2D 24
+#define CLK_CE 25
+#define CLK_BUS_CE 26
+#define CLK_VE 27
+#define CLK_BUS_VE 28
+#define CLK_EISE 29
+#define CLK_BUS_EISE 30
+#define CLK_NPU 31
+#define CLK_BUS_NPU 32
+#define CLK_BUS_DMA 33
+#define CLK_BUS_HSTIMER 34
+#define CLK_AVS 35
+#define CLK_BUS_DBG 36
+#define CLK_BUS_PSI 37
+#define CLK_BUS_PWM 38
+#define CLK_MBUS_DMA 40
+#define CLK_MBUS_VE 41
+#define CLK_MBUS_CE 42
+#define CLK_MBUS_TS 43
+#define CLK_MBUS_NAND 44
+#define CLK_MBUS_G2D 45
+#define CLK_MBUS_EISE 46
+#define CLK_MBUS_VDPO 47
+#define CLK_MMC0 49
+#define CLK_MMC1 50
+#define CLK_MMC2 51
+#define CLK_BUS_MMC0 52
+#define CLK_BUS_MMC1 53
+#define CLK_BUS_MMC2 54
+#define CLK_BUS_UART0 55
+#define CLK_BUS_UART1 56
+#define CLK_BUS_UART2 57
+#define CLK_BUS_UART3 58
+#define CLK_BUS_I2C0 59
+#define CLK_BUS_I2C1 60
+#define CLK_BUS_I2C2 61
+#define CLK_BUS_I2C3 62
+#define CLK_SPI0 63
+#define CLK_SPI1 64
+#define CLK_SPI2 65
+#define CLK_BUS_SPI0 66
+#define CLK_BUS_SPI1 67
+#define CLK_BUS_SPI2 68
+#define CLK_EMAC_25M 69
+#define CLK_BUS_EMAC0 70
+#define CLK_BUS_GPADC 71
+#define CLK_BUS_THS 72
+#define CLK_I2S0 73
+#define CLK_I2S1 74
+#define CLK_BUS_I2S0 75
+#define CLK_BUS_I2S1 76
+#define CLK_AUDIO_CODEC_1X 77
+#define CLK_AUDIO_CODEC_4X 78
+#define CLK_BUS_AUDIO_CODEC 79
+#define CLK_USB_OHCI0 80
+#define CLK_USB_PHY0 81
+#define CLK_BUS_OHCI0 82
+#define CLK_BUS_EHCI0 83
+#define CLK_BUS_OTG 84
+#define CLK_MIPI_DSI_DPHY0_HS 85
+#define CLK_MIPI_DSI_HOST0 86
+#define CLK_BUS_MIPI_DSI 87
+#define CLK_BUS_TCON_TOP 88
+#define CLK_TCON_LCD0 89
+#define CLK_BUS_TCON_LCD0 90
+#define CLK_CSI_TOP 91
+#define CLK_CSI_MCLK0 92
+#define CLK_CSI_MCLK1 93
+#define CLK_ISP 94
+#define CLK_BUS_CSI 95
+#define CLK_DSPO 96
+#define CLK_BUS_DSPO 97
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_V833_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v833-ccu.h b/include/dt-bindings/reset/sun8i-v833-ccu.h
new file mode 100644
index 000000000000..fb2b0e3b287f
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-v833-ccu.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_V833_H_
+#define _DT_BINDINGS_RESET_SUN8I_V833_H_
+
+#define RST_MBUS 0
+#define RST_BUS_DE 1
+#define RST_BUS_G2D 2
+#define RST_BUS_CE 3
+#define RST_BUS_VE 4
+#define RST_BUS_EISE 5
+#define RST_BUS_NPU 6
+#define RST_BUS_DMA 7
+#define RST_BUS_HSTIMER 8
+#define RST_BUS_DBG 9
+#define RST_BUS_PSI 10
+#define RST_BUS_PWM 11
+#define RST_BUS_DRAM 12
+#define RST_BUS_MMC0 13
+#define RST_BUS_MMC1 14
+#define RST_BUS_MMC2 15
+#define RST_BUS_UART0 16
+#define RST_BUS_UART1 17
+#define RST_BUS_UART2 18
+#define RST_BUS_UART3 19
+#define RST_BUS_I2C0 20
+#define RST_BUS_I2C1 21
+#define RST_BUS_I2C2 22
+#define RST_BUS_I2C3 23
+#define RST_BUS_SPI0 24
+#define RST_BUS_SPI1 25
+#define RST_BUS_SPI2 26
+#define RST_BUS_EMAC0 27
+#define RST_BUS_GPADC 28
+#define RST_BUS_THS 29
+#define RST_BUS_I2S0 30
+#define RST_BUS_I2S1 31
+#define RST_BUS_AUDIO_CODEC 32
+#define RST_USB_PHY0 33
+#define RST_BUS_OHCI0 34
+#define RST_BUS_EHCI0 35
+#define RST_BUS_OTG 36
+#define RST_BUS_MIPI_DSI 37
+#define RST_BUS_TCON_TOP 38
+#define RST_BUS_TCON_LCD0 39
+#define RST_BUS_CSI 40
+#define RST_BUS_DSPO 41
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_V833_H_ */
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 03/12] clk: sunxi-ng: add CCU driver for V831/V833
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
2020-12-12 4:01 ` [RFC PATCH 01/12] dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU Icenowy Zheng
2020-12-12 4:03 ` [RFC PATCH 02/12] dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers Icenowy Zheng
@ 2020-12-12 4:03 ` Icenowy Zheng
2020-12-12 4:04 ` [RFC PATCH 04/12] dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl Icenowy Zheng
` (8 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:03 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng
V831/V833 are new chips from Allwinner targeting camera market. The
difference between them is similar to V3s/V3, the former one is a
reduced-pin package with co-packaged DDR2 and the latter one is a BGA
package w/o DRAM packaged in.
Add a CCU driver for them. As the user manual didn't have marks for
different chips (V831 and V833 shares the same user manual file), only
implementing a full-functional CCU driver with V833 compatible.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
There's a PLL that is called PLL_UNI in the user manual. However a duck
test shows that it is quite similar to PLL_PERI1 on other SoCs: it
functions as parent to some peripherals, occupies the same register
offset with PLL_PERI1 and have the same clock rate configuration with
PLL_PERI1. Here I called it as pll-uni to follow the official document,
but I doubt whether we should call it pll-periph1 to be consistent with
other SoCs.
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-v833.c | 930 ++++++++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-v833.h | 46 ++
4 files changed, 982 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v833.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v833.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index ce5f5847d5d3..eb038d0f48d7 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -77,6 +77,11 @@ config SUN8I_V3S_CCU
default MACH_SUN8I
depends on MACH_SUN8I || COMPILE_TEST
+config SUN8I_V833_CCU
+ bool "Support for the Allwinner V833 CCU"
+ default MACH_SUN8I
+ depends on MACH_SUN8I || COMPILE_TEST
+
config SUN8I_DE2_CCU
bool "Support for the Allwinner SoCs DE2 CCU"
default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 3eb5cff40eac..dd33aba983bb 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
obj-$(CONFIG_SUN8I_A83T_CCU) += ccu-sun8i-a83t.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
+obj-$(CONFIG_SUN8I_V833_CCU) += ccu-sun8i-v833.o
obj-$(CONFIG_SUN8I_DE2_CCU) += ccu-sun8i-de2.o
obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
obj-$(CONFIG_SUN8I_R40_CCU) += ccu-sun8i-r40.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v833.c b/drivers/clk/sunxi-ng/ccu-sun8i-v833.c
new file mode 100644
index 000000000000..c60178035117
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v833.c
@@ -0,0 +1,930 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Icenowy Zheng <icenowy@aosc.io>
+ * Based on the H616 CCU driver, which is:
+ * Copyright (c) 2020 Arm Ltd.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun8i-v833.h"
+
+/*
+ * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
+ * P should only be used for output frequencies lower than 288 MHz.
+ *
+ * For now we can just model it as a multiplier clock, and force P to /1.
+ *
+ * The M factor is present in the register's description, but not in the
+ * frequency formula, and it's documented as "M is only used for backdoor
+ * testing", so it's not modelled and then force to 0.
+ */
+#define SUN8I_V833_PLL_CPUX_REG 0x000
+static struct ccu_mult pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .common = {
+ .reg = 0x000,
+ .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
+ &ccu_mult_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
+#define SUN8I_V833_PLL_DDR0_REG 0x010
+static struct ccu_nkmp pll_ddr0_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .common = {
+ .reg = 0x010,
+ .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+#define SUN8I_V833_PLL_PERIPH0_REG 0x020
+static struct ccu_nkmp pll_periph0_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .fixed_post_div = 2,
+ .common = {
+ .reg = 0x020,
+ .features = CCU_FEATURE_FIXED_POSTDIV,
+ .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+#define SUN8I_V833_PLL_UNI_REG 0x028
+static struct ccu_nkmp pll_uni_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .fixed_post_div = 2,
+ .common = {
+ .reg = 0x028,
+ .features = CCU_FEATURE_FIXED_POSTDIV,
+ .hw.init = CLK_HW_INIT("pll-uni", "osc24M",
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/*
+ * For Video PLLs, the output divider is described as "used for testing"
+ * in the user manual. So it's not modelled and forced to 0.
+ */
+#define SUN8I_V833_PLL_VIDEO0_REG 0x040
+static struct ccu_nm pll_video0_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .fixed_post_div = 4,
+ .min_rate = 288000000,
+ .max_rate = 2400000000UL,
+ .common = {
+ .reg = 0x040,
+ .features = CCU_FEATURE_FIXED_POSTDIV,
+ .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
+ &ccu_nm_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/*
+ * The Audio PLL is supposed to have 3 outputs: 2 fixed factors from
+ * the base (2x and 4x), and one variable divider (the one true pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names.
+ */
+#define SUN8I_V833_PLL_AUDIO_REG 0x078
+
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+ { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },
+ { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },
+};
+
+static struct ccu_nm pll_audio_base_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
+ BIT(24), 0x178, BIT(31)),
+ .common = {
+ .features = CCU_FEATURE_SIGMA_DELTA_MOD,
+ .reg = 0x078,
+ .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
+ &ccu_nm_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+#define SUN8I_V833_PLL_CSI_REG 0x0e0
+static struct ccu_nkmp pll_csi_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .common = {
+ .reg = 0x0e0,
+ .hw.init = CLK_HW_INIT("pll-csi", "osc24M",
+ &ccu_nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+static const char * const cpux_parents[] = { "osc24M", "osc32k",
+ "iosc", "pll-cpux", "pll-periph0" };
+static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
+ 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
+static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
+static struct clk_div_table cpux_apb_div_table[] = {
+ { .val = 0, .div = 1 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 4 },
+ { /* Sentinel */ },
+};
+static SUNXI_CCU_DIV_TABLE(cpux_apb_clk, "cpux-apb", "cpux",
+ 0x500, 8, 2, cpux_apb_div_table, 0);
+
+static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
+ "iosc", "pll-periph0" };
+static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
+ psi_ahb1_ahb2_parents,
+ 0x510,
+ 0, 2, /* M */
+ 8, 2, /* P */
+ 24, 2, /* mux */
+ 0);
+
+static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
+ "psi-ahb1-ahb2",
+ "pll-periph0" };
+static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
+ 0, 2, /* M */
+ 8, 2, /* P */
+ 24, 2, /* mux */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
+ 0, 2, /* M */
+ 8, 2, /* P */
+ 24, 2, /* mux */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
+ 0, 2, /* M */
+ 8, 2, /* P */
+ 24, 2, /* mux */
+ 0);
+
+static const char * const de_parents[] = { "pll-uni", "pll-uni-2x", "pll-periph0-2x" };
+static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
+ 0, 4, /* M */
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
+ 0x60c, BIT(0), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d", de_parents, 0x630,
+ 0, 4, /* M */
+ 24, 1, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
+ 0x63c, BIT(0), 0);
+
+static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 1, /* mux */
+ BIT(31),/* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
+ 0x68c, BIT(0), 0);
+
+static const char * const ve_eise_parents[] = { "pll-uni", "pll-uni-2x",
+ "pll-periph0", "pll-video0-4x" };
+static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_eise_parents, 0x690,
+ 0, 3, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
+ 0x69c, BIT(0), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(eise_clk, "eise", ve_eise_parents, 0x6d0,
+ 0, 3, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_eise_clk, "bus-eise", "psi-ahb1-ahb2",
+ 0x6dc, BIT(0), 0);
+
+static const char * const npu_parents[] = { "pll-periph0", "pll-periph0-2x",
+ "pll-uni", "pll-uni-2x",
+ "pll-video-4x", "pll-cpu",
+ "pll-csi" };
+static SUNXI_CCU_M_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0,
+ 0, 3, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+/*
+ * The bus that NPU is located is not specified on the user manual. Parent
+ * clock here is a guess based on the clock register is among other AHB1
+ * clocks.
+ */
+static SUNXI_CCU_GATE(bus_npu_clk, "bus-npu", "psi-ahb1-ahb2",
+ 0x6ec, BIT(0), 0);
+
+static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
+ 0x70c, BIT(0), 0);
+
+static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
+ 0x73c, BIT(0), 0);
+
+static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
+
+static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
+ 0x78c, BIT(0), 0);
+
+static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
+ 0x79c, BIT(0), 0);
+
+static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
+
+/*
+ * BSP kernel declares an IOMMU bus gate at 0x7bc, however the user manual
+ * does not mention it. By trying to poke registers, even if 0x7bc is 0,
+ * the IOMMU registers are accessible.
+ */
+
+static const char * const dram_parents[] = { "pll-ddr0", "pll-periph0-2x" };
+static struct ccu_div dram_clk = {
+ .div = _SUNXI_CCU_DIV(0, 2),
+ .mux = _SUNXI_CCU_MUX(24, 2),
+ .common = {
+ .reg = 0x800,
+ .hw.init = CLK_HW_INIT_PARENTS("dram",
+ dram_parents,
+ &ccu_div_ops,
+ CLK_IS_CRITICAL),
+ },
+};
+
+static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "psi-ahb1-ahb2",
+ 0x804, BIT(0), 0);
+static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "psi-ahb1-ahb2",
+ 0x804, BIT(1), 0);
+static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "psi-ahb1-ahb2",
+ 0x804, BIT(2), 0);
+static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-csi", "psi-ahb1-ahb2",
+ 0x804, BIT(8), 0);
+static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-isp", "psi-ahb1-ahb2",
+ 0x804, BIT(9), 0);
+static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "psi-ahb1-ahb2",
+ 0x804, BIT(10), 0);
+static SUNXI_CCU_GATE(mbus_eise_clk, "mbus-eise", "psi-ahb1-ahb2",
+ 0x804, BIT(23), 0);
+static SUNXI_CCU_GATE(mbus_vdpo_clk, "mbus-vdpo", "psi-ahb1-ahb2",
+ 0x804, BIT(27), 0);
+
+static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
+ 0x80c, BIT(0), CLK_IS_CRITICAL);
+
+static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
+ "pll-uni-2x" };
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 2, /* post-div */
+ 0);
+
+static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
+
+static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
+
+static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
+
+static const char * const spi_parents[] = { "osc24M", "pll-periph0",
+ "pll-uni", "pll-periph0-2x",
+ "pll-uni-2x" };
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 3, /* mux */
+ BIT(31),/* gate */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 3, /* mux */
+ BIT(31),/* gate */
+ 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 3, /* mux */
+ BIT(31),/* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb3", 0x96c, BIT(2), 0);
+
+static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
+ BIT(31) | BIT(30), 0);
+
+static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
+
+static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
+
+static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
+
+static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x",
+ "pll-audio-4x" };
+static struct ccu_div i2s0_clk = {
+ .enable = BIT(31),
+ .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+ .mux = _SUNXI_CCU_MUX(24, 2),
+ .common = {
+ .reg = 0xa10,
+ .hw.init = CLK_HW_INIT_PARENTS("i2s0",
+ audio_parents,
+ &ccu_div_ops,
+ CLK_SET_RATE_PARENT),
+ },
+};
+
+static struct ccu_div i2s1_clk = {
+ .enable = BIT(31),
+ .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
+ .mux = _SUNXI_CCU_MUX(24, 2),
+ .common = {
+ .reg = 0xa14,
+ .hw.init = CLK_HW_INIT_PARENTS("i2s1",
+ audio_parents,
+ &ccu_div_ops,
+ CLK_SET_RATE_PARENT),
+ },
+};
+
+static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa2c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa2c, BIT(1), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x",
+ audio_parents, 0xa50,
+ 0, 4, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
+ audio_parents, 0xa54,
+ 0, 4, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
+ BIT(0), 0);
+
+/*
+ * There are OHCI 12M clock source selection bits for the USB 2.0 port.
+ * We will force them to 0 (12M divided from 48M).
+ */
+#define SUN8I_V833_USB0_CLK_REG 0xa70
+
+static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
+static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
+
+static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
+static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
+
+static const char * const mipi_dsi_dphy0_hs_parents[] = { "pll-video0",
+ "pll-video0-4x" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mipi_dsi_dphy0_hs_clk, "mipi-dsi-dphy0-hs",
+ mipi_dsi_dphy0_hs_parents,
+ 0xb20,
+ 0, 4, /* M */
+ 8, 2, /* N */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const char * const mipi_dsi_host0_parents[] = { "pll-periph0",
+ "pll-periph0-4x",
+ "osc24M" };
+static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_host0_clk, "mipi-dsi-host0",
+ mipi_dsi_host0_parents,
+ 0xb24,
+ 0, 4, /* M */
+ 24, 2, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb3", 0xb4c, BIT(0), 0);
+
+static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
+ 0xb5c, BIT(0), 0);
+
+static const char * const tcon_lcd0_parents[] = { "pll-video0",
+ "pll-video0-4x" };
+static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
+ tcon_lcd0_parents, 0xb60,
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
+ 0xb7c, BIT(0), 0);
+
+static const char * const csi_top_parents[] = { "pll-uni", "pll-uni-2x",
+ "pll-periph0", "pll-periph0-2x",
+ "pll-video0-4x", "pll-csi" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_top_clk, "csi-top",
+ csi_top_parents, 0xc04,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const char * const csi_mclk_parents[] = { "osc24M", "pll-uni",
+ "pll-uni-2x", "pll-periph0",
+ "pll-periph0-2x", "pll-video0",
+ "pll-csi" };
+
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk0_clk, "csi-mclk0",
+ csi_mclk_parents, 0xc08,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk1_clk, "csi-mclk1",
+ csi_mclk_parents, 0xc0c,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static const char * const isp_parents[] = { "pll-uni", "pll-uni-2x",
+ "pll-periph0", "pll-video0-4x",
+ "pll-csi" };
+static SUNXI_CCU_M_WITH_MUX_GATE(isp_clk, "isp",
+ isp_parents, 0xc20,
+ 0, 5, /* M */
+ 24, 3, /* mux */
+ BIT(31), /* gate */
+ 0);
+
+static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
+
+static const char * const dspo_parents[] = { "pll-video0", "pll-video0-4x",
+ "pll-periph0", "pll-periph0-2x",
+ "pll-uni", "pll-uni-2x",
+ "pll-csi" };
+static SUNXI_CCU_MP_WITH_MUX(dspo_clk, "dspo",
+ dspo_parents,
+ 0xc60,
+ 0, 2, /* M */
+ 8, 2, /* P */
+ 24, 2, /* mux */
+ 0);
+
+static SUNXI_CCU_GATE(bus_dspo_clk, "bus-dspo", "ahb3", 0xc6c, BIT(0), 0);
+
+/* Fixed factor clocks */
+static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
+
+static const struct clk_hw *clk_parent_pll_audio[] = {
+ &pll_audio_base_clk.common.hw
+};
+
+/*
+ * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
+ * rates can be set exactly in conjunction with sigma-delta modulation.
+ */
+static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ clk_parent_pll_audio,
+ 24, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ clk_parent_pll_audio,
+ 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
+ clk_parent_pll_audio,
+ 2, 1, CLK_SET_RATE_PARENT);
+
+static const struct clk_hw *pll_periph0_parents[] = {
+ &pll_periph0_clk.common.hw
+};
+
+static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
+ pll_periph0_parents,
+ 1, 2, 0);
+
+static const struct clk_hw *pll_uni_parents[] = {
+ &pll_uni_clk.common.hw
+};
+
+static CLK_FIXED_FACTOR_HWS(pll_uni_2x_clk, "pll-uni-2x",
+ pll_uni_parents,
+ 1, 2, 0);
+
+static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
+ &pll_video0_clk.common.hw,
+ 1, 4, CLK_SET_RATE_PARENT);
+
+static struct ccu_common *sun8i_v833_ccu_clks[] = {
+ &pll_cpux_clk.common,
+ &pll_ddr0_clk.common,
+ &pll_periph0_clk.common,
+ &pll_uni_clk.common,
+ &pll_video0_clk.common,
+ &pll_audio_base_clk.common,
+ &pll_csi_clk.common,
+ &cpux_clk.common,
+ &axi_clk.common,
+ &cpux_apb_clk.common,
+ &psi_ahb1_ahb2_clk.common,
+ &ahb3_clk.common,
+ &apb1_clk.common,
+ &apb2_clk.common,
+ &de_clk.common,
+ &bus_de_clk.common,
+ &g2d_clk.common,
+ &bus_g2d_clk.common,
+ &ce_clk.common,
+ &bus_ce_clk.common,
+ &ve_clk.common,
+ &bus_ve_clk.common,
+ &eise_clk.common,
+ &bus_eise_clk.common,
+ &npu_clk.common,
+ &bus_npu_clk.common,
+ &bus_dma_clk.common,
+ &bus_hstimer_clk.common,
+ &avs_clk.common,
+ &bus_dbg_clk.common,
+ &bus_psi_clk.common,
+ &bus_pwm_clk.common,
+ &dram_clk.common,
+ &mbus_dma_clk.common,
+ &mbus_ve_clk.common,
+ &mbus_ce_clk.common,
+ &mbus_ts_clk.common,
+ &mbus_nand_clk.common,
+ &mbus_g2d_clk.common,
+ &mbus_eise_clk.common,
+ &mbus_vdpo_clk.common,
+ &bus_dram_clk.common,
+ &mmc0_clk.common,
+ &mmc1_clk.common,
+ &mmc2_clk.common,
+ &bus_mmc0_clk.common,
+ &bus_mmc1_clk.common,
+ &bus_mmc2_clk.common,
+ &bus_uart0_clk.common,
+ &bus_uart1_clk.common,
+ &bus_uart2_clk.common,
+ &bus_uart3_clk.common,
+ &bus_i2c0_clk.common,
+ &bus_i2c1_clk.common,
+ &bus_i2c2_clk.common,
+ &bus_i2c3_clk.common,
+ &spi0_clk.common,
+ &spi1_clk.common,
+ &spi2_clk.common,
+ &bus_spi0_clk.common,
+ &bus_spi1_clk.common,
+ &bus_spi2_clk.common,
+ &emac_25m_clk.common,
+ &bus_emac0_clk.common,
+ &bus_gpadc_clk.common,
+ &bus_ths_clk.common,
+ &i2s0_clk.common,
+ &i2s1_clk.common,
+ &bus_i2s0_clk.common,
+ &bus_i2s1_clk.common,
+ &audio_codec_1x_clk.common,
+ &audio_codec_4x_clk.common,
+ &bus_audio_codec_clk.common,
+ &usb_ohci0_clk.common,
+ &usb_phy0_clk.common,
+ &bus_ohci0_clk.common,
+ &bus_ehci0_clk.common,
+ &bus_otg_clk.common,
+ &mipi_dsi_dphy0_hs_clk.common,
+ &mipi_dsi_host0_clk.common,
+ &bus_mipi_dsi_clk.common,
+ &bus_tcon_top_clk.common,
+ &tcon_lcd0_clk.common,
+ &bus_tcon_lcd0_clk.common,
+ &csi_top_clk.common,
+ &csi_mclk0_clk.common,
+ &csi_mclk1_clk.common,
+ &isp_clk.common,
+ &bus_csi_clk.common,
+ &dspo_clk.common,
+ &bus_dspo_clk.common,
+};
+
+static struct clk_hw_onecell_data sun8i_v833_hw_clks = {
+ .hws = {
+ [CLK_OSC12M] = &osc12M_clk.hw,
+ [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
+ [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
+ [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
+ [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
+ [CLK_PLL_UNI] = &pll_uni_clk.common.hw,
+ [CLK_PLL_UNI_2X] = &pll_uni_2x_clk.hw,
+ [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
+ [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
+ [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
+ [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
+ [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
+ [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
+ [CLK_PLL_CSI] = &pll_csi_clk.common.hw,
+ [CLK_CPUX] = &cpux_clk.common.hw,
+ [CLK_AXI] = &axi_clk.common.hw,
+ [CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
+ [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
+ [CLK_AHB3] = &ahb3_clk.common.hw,
+ [CLK_APB1] = &apb1_clk.common.hw,
+ [CLK_APB2] = &apb2_clk.common.hw,
+ [CLK_DE] = &de_clk.common.hw,
+ [CLK_BUS_DE] = &bus_de_clk.common.hw,
+ [CLK_G2D] = &g2d_clk.common.hw,
+ [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
+ [CLK_CE] = &ce_clk.common.hw,
+ [CLK_BUS_CE] = &bus_ce_clk.common.hw,
+ [CLK_VE] = &ve_clk.common.hw,
+ [CLK_BUS_VE] = &bus_ve_clk.common.hw,
+ [CLK_EISE] = &eise_clk.common.hw,
+ [CLK_BUS_EISE] = &bus_eise_clk.common.hw,
+ [CLK_NPU] = &npu_clk.common.hw,
+ [CLK_BUS_NPU] = &bus_npu_clk.common.hw,
+ [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
+ [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
+ [CLK_AVS] = &avs_clk.common.hw,
+ [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
+ [CLK_BUS_PSI] = &bus_psi_clk.common.hw,
+ [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
+ [CLK_DRAM] = &dram_clk.common.hw,
+ [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
+ [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
+ [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
+ [CLK_MBUS_TS] = &mbus_ts_clk.common.hw,
+ [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
+ [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
+ [CLK_MBUS_EISE] = &mbus_eise_clk.common.hw,
+ [CLK_MBUS_VDPO] = &mbus_vdpo_clk.common.hw,
+ [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
+ [CLK_MMC0] = &mmc0_clk.common.hw,
+ [CLK_MMC1] = &mmc1_clk.common.hw,
+ [CLK_MMC2] = &mmc2_clk.common.hw,
+ [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
+ [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
+ [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
+ [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
+ [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
+ [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
+ [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
+ [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
+ [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
+ [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
+ [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
+ [CLK_SPI0] = &spi0_clk.common.hw,
+ [CLK_SPI1] = &spi1_clk.common.hw,
+ [CLK_SPI2] = &spi2_clk.common.hw,
+ [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
+ [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
+ [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
+ [CLK_EMAC_25M] = &emac_25m_clk.common.hw,
+ [CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw,
+ [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
+ [CLK_BUS_THS] = &bus_ths_clk.common.hw,
+ [CLK_I2S0] = &i2s0_clk.common.hw,
+ [CLK_I2S1] = &i2s1_clk.common.hw,
+ [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
+ [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
+ [CLK_AUDIO_CODEC_1X] = &audio_codec_1x_clk.common.hw,
+ [CLK_AUDIO_CODEC_4X] = &audio_codec_4x_clk.common.hw,
+ [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
+ [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
+ [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
+ [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
+ [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
+ [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
+ [CLK_MIPI_DSI_DPHY0_HS] = &mipi_dsi_dphy0_hs_clk.common.hw,
+ [CLK_MIPI_DSI_HOST0] = &mipi_dsi_host0_clk.common.hw,
+ [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
+ [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
+ [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
+ [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
+ [CLK_CSI_TOP] = &csi_top_clk.common.hw,
+ [CLK_CSI_MCLK0] = &csi_mclk0_clk.common.hw,
+ [CLK_CSI_MCLK1] = &csi_mclk1_clk.common.hw,
+ [CLK_ISP] = &isp_clk.common.hw,
+ [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
+ [CLK_DSPO] = &dspo_clk.common.hw,
+ [CLK_BUS_DSPO] = &bus_dspo_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun8i_v833_ccu_resets[] = {
+ [RST_MBUS] = { 0x540, BIT(30) },
+
+ [RST_BUS_DE] = { 0x60c, BIT(16) },
+ [RST_BUS_G2D] = { 0x63c, BIT(16) },
+ [RST_BUS_CE] = { 0x68c, BIT(16) },
+ [RST_BUS_VE] = { 0x69c, BIT(16) },
+ [RST_BUS_EISE] = { 0x6dc, BIT(16) },
+ [RST_BUS_NPU] = { 0x6ec, BIT(16) },
+ [RST_BUS_DMA] = { 0x70c, BIT(16) },
+ [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
+ [RST_BUS_DBG] = { 0x78c, BIT(16) },
+ [RST_BUS_PSI] = { 0x79c, BIT(16) },
+ [RST_BUS_PWM] = { 0x7ac, BIT(16) },
+ [RST_BUS_DRAM] = { 0x70c, BIT(16) },
+ [RST_BUS_MMC0] = { 0x84c, BIT(16) },
+ [RST_BUS_MMC1] = { 0x84c, BIT(17) },
+ [RST_BUS_MMC2] = { 0x84c, BIT(18) },
+ [RST_BUS_UART0] = { 0x90c, BIT(16) },
+ [RST_BUS_UART1] = { 0x90c, BIT(17) },
+ [RST_BUS_UART2] = { 0x90c, BIT(18) },
+ [RST_BUS_UART3] = { 0x90c, BIT(19) },
+ [RST_BUS_I2C0] = { 0x91c, BIT(16) },
+ [RST_BUS_I2C1] = { 0x91c, BIT(17) },
+ [RST_BUS_I2C2] = { 0x91c, BIT(18) },
+ [RST_BUS_I2C3] = { 0x91c, BIT(19) },
+ [RST_BUS_SPI0] = { 0x96c, BIT(16) },
+ [RST_BUS_SPI1] = { 0x96c, BIT(17) },
+ [RST_BUS_SPI2] = { 0x96c, BIT(18) },
+ [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
+ [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
+ [RST_BUS_THS] = { 0x9fc, BIT(16) },
+ [RST_BUS_I2S0] = { 0xa2c, BIT(16) },
+ [RST_BUS_I2S1] = { 0xa2c, BIT(17) },
+ [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
+
+ [RST_USB_PHY0] = { 0xa70, BIT(30) },
+
+ [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
+ [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
+ [RST_BUS_OTG] = { 0xa8c, BIT(24) },
+ [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
+ [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
+ [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
+ [RST_BUS_CSI] = { 0xc2c, BIT(16) },
+ [RST_BUS_DSPO] = { 0xc6c, BIT(16) },
+};
+
+static const struct sunxi_ccu_desc sun8i_v833_ccu_desc = {
+ .ccu_clks = sun8i_v833_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_v833_ccu_clks),
+
+ .hw_clks = &sun8i_v833_hw_clks,
+
+ .resets = sun8i_v833_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun8i_v833_ccu_resets),
+};
+
+static const u32 pll_regs[] = {
+ SUN8I_V833_PLL_CPUX_REG,
+ SUN8I_V833_PLL_DDR0_REG,
+ SUN8I_V833_PLL_PERIPH0_REG,
+ SUN8I_V833_PLL_UNI_REG,
+ SUN8I_V833_PLL_VIDEO0_REG,
+ SUN8I_V833_PLL_AUDIO_REG,
+ SUN8I_V833_PLL_CSI_REG,
+};
+
+static const u32 pll_video_regs[] = {
+ SUN8I_V833_PLL_VIDEO0_REG,
+};
+
+static void __init sun8i_v833_ccu_setup(struct device_node *node)
+{
+ void __iomem *reg;
+ u32 val;
+ int i;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err("%pOF: Could not map clock registers\n", node);
+ return;
+ }
+
+ /* Enable the lock bits and the output enable bits on all PLLs */
+ for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
+ val = readl(reg + pll_regs[i]);
+ val |= BIT(29) | BIT(27);
+ writel(val, reg + pll_regs[i]);
+ }
+
+ /*
+ * Force the output divider of pll-video0 to 0.
+ *
+ * See the comment before its definition for the reason.
+ */
+ val = readl(reg + SUN8I_V833_PLL_VIDEO0_REG);
+ val &= ~BIT(0);
+ writel(val, reg + SUN8I_V833_PLL_VIDEO0_REG);
+
+ /*
+ * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
+ *
+ * This clock mux is still mysterious, and the code just enforces
+ * it to have a valid clock parent.
+ */
+ val = readl(reg + SUN8I_V833_USB0_CLK_REG);
+ val &= ~GENMASK(25, 24);
+ writel(val, reg + SUN8I_V833_USB0_CLK_REG);
+
+ /*
+ * Force the post-divider of pll-audio to 12 and the output divider
+ * of it to 2, so 24576000 and 22579200 rates can be set exactly.
+ */
+ val = readl(reg + SUN8I_V833_PLL_AUDIO_REG);
+ val &= ~(GENMASK(21, 16) | BIT(0));
+ writel(val | (11 << 16) | BIT(0), reg + SUN8I_V833_PLL_AUDIO_REG);
+
+ i = sunxi_ccu_probe(node, reg, &sun8i_v833_ccu_desc);
+ if (i)
+ pr_err("%pOF: probing clocks fails: %d\n", node, i);
+}
+
+CLK_OF_DECLARE(sun8i_v833_ccu, "allwinner,sun8i-v833-ccu",
+ sun8i_v833_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v833.h b/drivers/clk/sunxi-ng/ccu-sun8i-v833.h
new file mode 100644
index 000000000000..75188c446ac6
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v833.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _CCU_SUN8I_V833_H_
+#define _CCU_SUN8I_V833_H_
+
+#include <dt-bindings/clock/sun8i-v833-ccu.h>
+#include <dt-bindings/reset/sun8i-v833-ccu.h>
+
+#define CLK_OSC12M 0
+#define CLK_PLL_CPUX 1
+#define CLK_PLL_DDR0 2
+#define CLK_PLL_PERIPH0 3
+#define CLK_PLL_PERIPH0_2X 4
+#define CLK_PLL_UNI 5
+#define CLK_PLL_UNI_2X 6
+#define CLK_PLL_VIDEO0 7
+#define CLK_PLL_VIDEO0_4X 8
+#define CLK_PLL_AUDIO_BASE 9
+#define CLK_PLL_AUDIO 10
+#define CLK_PLL_AUDIO_2X 11
+#define CLK_PLL_AUDIO_4X 12
+#define CLK_PLL_CSI 13
+
+/* CPUX clock exported for DVFS */
+
+#define CLK_AXI 15
+#define CLK_CPUX_APB 16
+#define CLK_PSI_AHB1_AHB2 17
+#define CLK_AHB3 18
+
+/* APB1 clock exported for PIO */
+
+#define CLK_APB2 20
+
+/* All module clocks and bus gates are exported except DRAM */
+
+#define CLK_DRAM 39
+
+#define CLK_BUS_DRAM 48
+
+#define CLK_NUMBER (CLK_BUS_DSPO + 1)
+
+#endif /* _CCU_SUN8I_V833_H_ */
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 04/12] dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (2 preceding siblings ...)
2020-12-12 4:03 ` [RFC PATCH 03/12] clk: sunxi-ng: add CCU driver for V831/V833 Icenowy Zheng
@ 2020-12-12 4:04 ` Icenowy Zheng
2020-12-15 16:18 ` Rob Herring
2020-12-12 4:04 ` [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833 Icenowy Zheng
` (7 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:04 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng,
Linus Walleij, linux-gpio
V831/V833 are a pair of new Allwinner chips. The difference between them
is similar to V3s/V3, but the chip design is similar to newer Allwinner
chips started from H6.
Add compatible strings for V831/V833 pinctrl.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 5240487dfe50..3d6855856594 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -44,6 +44,8 @@ properties:
- allwinner,sun8i-r40-pinctrl
- allwinner,sun8i-v3-pinctrl
- allwinner,sun8i-v3s-pinctrl
+ - allwinner,sun8i-v831-pinctrl
+ - allwinner,sun8i-v833-pinctrl
- allwinner,sun9i-a80-pinctrl
- allwinner,sun9i-a80-r-pinctrl
- allwinner,sun50i-a64-pinctrl
@@ -189,6 +191,8 @@ allOf:
enum:
- allwinner,sun8i-a23-pinctrl
- allwinner,sun8i-a83t-pinctrl
+ - allwinner,sun8i-v831-pinctrl
+ - allwinner,sun8i-v833-pinctrl
- allwinner,sun50i-a64-pinctrl
- allwinner,sun50i-h5-pinctrl
- allwinner,suniv-f1c100s-pinctrl
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (3 preceding siblings ...)
2020-12-12 4:04 ` [RFC PATCH 04/12] dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl Icenowy Zheng
@ 2020-12-12 4:04 ` Icenowy Zheng
2020-12-14 14:21 ` Maxime Ripard
2021-01-04 14:47 ` Linus Walleij
2020-12-12 4:06 ` [RFC PATCH 06/12] dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC Icenowy Zheng
` (6 subsequent siblings)
11 siblings, 2 replies; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:04 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng,
Linus Walleij, linux-gpio
V831/V833 are new chips from Allwinner. They're the same die with
different package.
Add a pinctrl driver for them.
The difference between V831/V833 pinctrl is implemented based on the
user manual.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c | 743 +++++++++++++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
4 files changed, 751 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 593293584ecc..fc13335a3eda 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -73,6 +73,11 @@ config PINCTRL_SUN8I_V3S
default MACH_SUN8I
select PINCTRL_SUNXI
+config PINCTRL_SUN8I_V83X
+ bool "Support for the Allwinner V831/V833 PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
config PINCTRL_SUN9I_A80
bool "Support for the Allwinner A80 PIO"
default MACH_SUN9I
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 8b7ff0dc3bdf..8bcca109e942 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
+obj-$(CONFIG_PINCTRL_SUN8I_V83X) += pinctrl-sun8i-v83x.o
obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
new file mode 100644
index 000000000000..19d035dcebbf
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
@@ -0,0 +1,743 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_v83x_pins[] = {
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "mmc2", /* DS */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "mmc2", /* RST */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "mmc2", /* CLK */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "mmc2", /* CMD */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "mmc2", /* WP */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x4, "spi0"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "mmc2", /* HOLD */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x4, "spi0"), /* D4 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 11),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
+ /* Hole */
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 0 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D0 */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D4 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 1 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D1 */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 2 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D2 */
+ SUNXI_FUNCTION(0x5, "emac"), /* CRS_DV */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 3 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D3 */
+ SUNXI_FUNCTION(0x5, "emac"), /* RXER */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 4 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D4 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 5 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D5 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 6 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D6 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 7 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D7 */
+ SUNXI_FUNCTION(0x5, "emac"), /* TXEN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
+ SUNXI_FUNCTION(0x3, "pwm"), /* 8 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "vo"), /* D8 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
+ SUNXI_FUNCTION(0x4, "vo"), /* D9 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
+ SUNXI_FUNCTION(0x4, "vo"), /* D10 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT0 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D11 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
+ SUNXI_FUNCTION(0x3, "i2s1_out"), /* DOUT1 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D11 */
+ SUNXI_FUNCTION(0x5, "i2s1_in"), /* DIN1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
+ SUNXI_FUNCTION(0x3, "i2s1_out"), /* DOUT2 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D13 */
+ SUNXI_FUNCTION(0x5, "i2s1_in"), /* DIN2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
+ SUNXI_FUNCTION(0x3, "i2s1_out"), /* DOUT3 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D14 */
+ SUNXI_FUNCTION(0x5, "i2s1_in"), /* DIN3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
+ SUNXI_FUNCTION(0x3, "i2s1"), /* DIN0 */
+ SUNXI_FUNCTION(0x4, "vo"), /* D15 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
+ SUNXI_FUNCTION(0x4, "vo"), /* CLK */
+ SUNXI_FUNCTION(0x5, "emac"), /* EPHY_25M */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* DE */
+ SUNXI_FUNCTION(0x4, "vo"), /* FIELD */
+ SUNXI_FUNCTION(0x5, "tcon_trig"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "vo"), /* HSYNC */
+ SUNXI_FUNCTION(0x5, "emac"), /* MDC */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
+ SUNXI_FUNCTION(0x4, "vo"), /* VSYNC */
+ SUNXI_FUNCTION(0x5, "emac"), /* MDIO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 22),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 9 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)),
+ /* Hole */
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 0),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* PCLK */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 1),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 2),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 3),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 4),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D0 */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 5),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D1 */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXCTL */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 6),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D2 */
+ SUNXI_FUNCTION(0x3, "emac"), /* CLKIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 7),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D3 */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 8),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D4 */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 9),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D5 */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 10),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D6 */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 11),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D7 */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 12),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D8 */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXCTL */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 13),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D9 */
+ SUNXI_FUNCTION(0x3, "emac"), /* MDC */
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 14),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D10 */
+ SUNXI_FUNCTION(0x3, "emac"), /* MDIO */
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 15),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1_data"), /* D11 */
+ SUNXI_FUNCTION(0x3, "emac"), /* EPHY_25M */
+ SUNXI_FUNCTION(0x3, "csi1_field"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "lcd", /* D0 */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_VARIANT(0x3,
+ "lcd", /* D1 */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 18),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D12 */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
+ SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
+ SUNXI_FUNCTION(0x5, "uart2"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 19),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D13 */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
+ SUNXI_FUNCTION(0x4, "spi2"), /* MOSI */
+ SUNXI_FUNCTION(0x5, "uart2"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 20),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D14 */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
+ SUNXI_FUNCTION(0x4, "spi2"), /* MISO */
+ SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(E, 21),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi1"), /* D15 */
+ SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
+ SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
+ SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS */
+ SUNXI_FUNCTION(0x5, "cpu_bist0"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI */
+ SUNXI_FUNCTION(0x5, "cpu_bist1"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION(0x5, "uart3"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION(0x5, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION(0x5, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION(0x5, "uart3"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x5, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x5, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 7)),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 0 */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x5, "uart3"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 1 */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x5, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 2 */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x5, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 3 */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x5, "uart3"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 4 */
+ SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS1 */
+ SUNXI_FUNCTION(0x5, "w1"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 5 */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD1 */
+ SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
+ SUNXI_FUNCTION(0x5, "uart2"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 6 */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXD0 */
+ SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
+ SUNXI_FUNCTION(0x5, "uart2"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 7 */
+ SUNXI_FUNCTION(0x3, "emac"), /* CRS_DV */
+ SUNXI_FUNCTION(0x4, "uart0"), /* TX */
+ SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 8 */
+ SUNXI_FUNCTION(0x3, "emac"), /* RXER */
+ SUNXI_FUNCTION(0x4, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm"), /* 9 */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD1 */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
+ SUNXI_FUNCTION(0x5, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* TXD0 */
+ SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
+ SUNXI_FUNCTION(0x5, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "jtag"), /* MS */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXCK */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "jtag"), /* CK */
+ SUNXI_FUNCTION(0x3, "emac"), /* TXEN */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "jtag"), /* DO */
+ SUNXI_FUNCTION(0x3, "emac"), /* MDC */
+ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x5, "i2c3"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "jtag"), /* DI */
+ SUNXI_FUNCTION(0x3, "emac"), /* MDIO */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x5, "i2c3"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(H, 15),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "emac"), /* EPHY_25M */
+ SUNXI_FUNCTION(0x4, "spi1"), /* CS1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* MCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* SM_HS */
+ SUNXI_FUNCTION_VARIANT(0x4,
+ "spi2", /* CLK */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi0"), /* SM_VS */
+ SUNXI_FUNCTION(0x3, "tcon_trig"),
+ SUNXI_FUNCTION_VARIANT(0x4,
+ "spi2", /* MOSI */
+ PINCTRL_SUN8I_V833),
+ SUNXI_FUNCTION(0x5, "i2c1"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(I, 3),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
+ SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
+ SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(I, 4),
+ PINCTRL_SUN8I_V833,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
+ SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
+};
+
+static const unsigned int sun8i_v83x_pinctrl_irq_bank_map[] = { 2, 3, 4, 5, 6, 7, 8 };
+
+static const struct sunxi_pinctrl_desc sun8i_v83x_pinctrl_data = {
+ .pins = sun8i_v83x_pins,
+ .npins = ARRAY_SIZE(sun8i_v83x_pins),
+ .irq_banks = 7,
+ .irq_bank_map = sun8i_v83x_pinctrl_irq_bank_map,
+ .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+};
+
+static int sun8i_v83x_pinctrl_probe(struct platform_device *pdev)
+{
+ unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev);
+
+ return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v83x_pinctrl_data,
+ variant);
+}
+
+static const struct of_device_id sun8i_v83x_pinctrl_match[] = {
+ {
+ .compatible = "allwinner,sun8i-v831-pinctrl",
+ .data = (void *)PINCTRL_SUN8I_V831
+ },
+ {
+ .compatible = "allwinner,sun8i-v833-pinctrl",
+ .data = (void *)PINCTRL_SUN8I_V833
+ },
+ { },
+};
+
+static struct platform_driver sun8i_v83x_pinctrl_driver = {
+ .probe = sun8i_v83x_pinctrl_probe,
+ .driver = {
+ .name = "sun8i-v83x-pinctrl",
+ .of_match_table = sun8i_v83x_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun8i_v83x_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a32bb5bcb754..b3b157dfc510 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -96,6 +96,8 @@
#define PINCTRL_SUN8I_R40 BIT(8)
#define PINCTRL_SUN8I_V3 BIT(9)
#define PINCTRL_SUN8I_V3S BIT(10)
+#define PINCTRL_SUN8I_V831 BIT(11)
+#define PINCTRL_SUN8I_V833 BIT(12)
#define PIO_POW_MOD_SEL_REG 0x340
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 06/12] dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (4 preceding siblings ...)
2020-12-12 4:04 ` [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833 Icenowy Zheng
@ 2020-12-12 4:06 ` Icenowy Zheng
2020-12-14 14:19 ` Rob Herring
2020-12-12 4:09 ` [RFC PATCH 07/12] " Icenowy Zheng
` (5 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:06 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng,
Alessandro Zummo, Alexandre Belloni, linux-rtc
V831/V833 SoCs (the same die) have a RTC block similar to the one in H6,
but allow to generate the osc32k clock from osc24M.
Add a new compatible string for that.
The functionality of dividing osc24M to generate osc32k is still TODO.
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: linux-rtc@vger.kernel.org
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
index 37c2a601c3fa..6e3a3b14db7b 100644
--- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
@@ -21,6 +21,7 @@ properties:
- const: allwinner,sun8i-h3-rtc
- const: allwinner,sun8i-r40-rtc
- const: allwinner,sun8i-v3-rtc
+ - const: allwinner,sun8i-v831-rtc
- const: allwinner,sun50i-h5-rtc
- items:
- const: allwinner,sun50i-a64-rtc
@@ -97,6 +98,7 @@ allOf:
properties:
compatible:
contains:
+ const: allwinner,sun8i-v831-rtc
const: allwinner,sun50i-h6-rtc
then:
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 07/12] rtc: sun6i: add compatible string for V831/V833 RTC
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (5 preceding siblings ...)
2020-12-12 4:06 ` [RFC PATCH 06/12] dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC Icenowy Zheng
@ 2020-12-12 4:09 ` Icenowy Zheng
2020-12-12 5:03 ` [RFC PATCH 08/12] dt-bindings: mmc: sunxi: add compatible strings for V831 MMC Icenowy Zheng
` (4 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 4:09 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng,
Alessandro Zummo, Alexandre Belloni, linux-rtc
These chips share the same die, and the RTC block is similar to H6
one, but with functionality of dividing 24M clock to get 32k (useful for
32k clock output).
Add compatible string for it. The special clock divider is TODO.
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: linux-rtc@vger.kernel.org
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/rtc/rtc-sun6i.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
index e2b8b150bcb4..c9a1f2319f92 100644
--- a/drivers/rtc/rtc-sun6i.c
+++ b/drivers/rtc/rtc-sun6i.c
@@ -378,6 +378,23 @@ static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
sun50i_h6_rtc_clk_init);
+static const struct sun6i_rtc_clk_data sun8i_v831_rtc_data = {
+ .rc_osc_rate = 16000000,
+ .fixed_prescaler = 32,
+ .has_prescaler = 1,
+ .has_out_clk = 1,
+ .export_iosc = 1,
+ .has_losc_en = 1,
+ .has_auto_swt = 1,
+};
+
+static void __init sun8i_v831_rtc_clk_init(struct device_node *node)
+{
+ sun6i_rtc_clk_init(node, &sun8i_v831_rtc_data);
+}
+CLK_OF_DECLARE_DRIVER(sun8i_v831_rtc_clk, "allwinner,sun8i-v831-rtc",
+ sun8i_v831_rtc_clk_init);
+
/*
* The R40 user manual is self-conflicting on whether the prescaler is
* fixed or configurable. The clock diagram shows it as fixed, but there
@@ -745,6 +762,7 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = {
{ .compatible = "allwinner,sun8i-h3-rtc" },
{ .compatible = "allwinner,sun8i-r40-rtc" },
{ .compatible = "allwinner,sun8i-v3-rtc" },
+ { .compatible = "allwinner,sun8i-v831-rtc" },
{ .compatible = "allwinner,sun50i-h5-rtc" },
{ .compatible = "allwinner,sun50i-h6-rtc" },
{ /* sentinel */ },
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 08/12] dt-bindings: mmc: sunxi: add compatible strings for V831 MMC
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (6 preceding siblings ...)
2020-12-12 4:09 ` [RFC PATCH 07/12] " Icenowy Zheng
@ 2020-12-12 5:03 ` Icenowy Zheng
2020-12-14 14:38 ` Maxime Ripard
2020-12-12 5:05 ` [RFC PATCH 09/12] dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT Icenowy Zheng
` (3 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 5:03 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng,
Ulf Hansson, linux-mmc
V831 has MMC controllers similar to the ones on H6.
Add a compatible string for them.
The eMMC controller compatible is not added, because the eMMC controller
is not available on V831, only V833.
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-mmc@vger.kernel.org
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
index e82c9a07b6fb..985586cb93b4 100644
--- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
+++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
@@ -35,6 +35,9 @@ properties:
- items:
- const: allwinner,sun8i-r40-mmc
- const: allwinner,sun50i-a64-mmc
+ - items:
+ - const: allwinner,sun8i-v831-mmc
+ - const: allwinner,sun50i-a64-mmc
- items:
- const: allwinner,sun50i-h5-emmc
- const: allwinner,sun50i-a64-emmc
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 09/12] dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (7 preceding siblings ...)
2020-12-12 5:03 ` [RFC PATCH 08/12] dt-bindings: mmc: sunxi: add compatible strings for V831 MMC Icenowy Zheng
@ 2020-12-12 5:05 ` Icenowy Zheng
2020-12-15 16:27 ` Rob Herring
2020-12-12 5:12 ` [RFC PATCH 10/12] dt-bindings: spi: sun6i: add compatible for V831 SPI Icenowy Zheng
` (2 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 5:05 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng,
Wim Van Sebroeck, Guenter Roeck, linux-watchdog
V831/V833 has a watchdog similar to the ones on previous Allwinner SoCs
after sun6i.
Add a compatible string for it.
Cc: Wim Van Sebroeck <wim@linux-watchdog.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: linux-watchdog@vger.kernel.org
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
index e8f226376108..2f3c350b0057 100644
--- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
@@ -18,6 +18,9 @@ properties:
oneOf:
- const: allwinner,sun4i-a10-wdt
- const: allwinner,sun6i-a31-wdt
+ - items:
+ - const: allwinner,sun8i-v831-wdt
+ - const: allwinner,sun6i-a31-wdt
- items:
- const: allwinner,sun50i-a64-wdt
- const: allwinner,sun6i-a31-wdt
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 10/12] dt-bindings: spi: sun6i: add compatible for V831 SPI
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (8 preceding siblings ...)
2020-12-12 5:05 ` [RFC PATCH 09/12] dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT Icenowy Zheng
@ 2020-12-12 5:12 ` Icenowy Zheng
2020-12-15 16:32 ` Rob Herring
2020-12-12 5:12 ` [RFC PATCH 11/12] ARM: dts: sun8i: add DTSI file for V831 Icenowy Zheng
2020-12-12 5:13 ` [RFC PATCH 12/12] [DO NOT MERGE] ARM: dts: sun8i: v831: add a device tree file for Y20GA Icenowy Zheng
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 5:12 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng,
Mark Brown, linux-spi
V831 has a SPI controller similar to the H6 one.
Add a compatible string for it.
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
H6 and V831 SPI controllers is not totally the same with H3: they have
QSPI support added. Here V831 compatible string is just added in
parallel with H6 one, but maybe we should make H6 SPI do not fallback to
H3 one, and add H6 one as fallback to V831?
.../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
index 7866a655d81c..a620ff30033e 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
@@ -24,6 +24,7 @@ properties:
- items:
- enum:
- allwinner,sun8i-r40-spi
+ - allwinner,sun8i-v831-spi
- allwinner,sun50i-h6-spi
- const: allwinner,sun8i-h3-spi
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 11/12] ARM: dts: sun8i: add DTSI file for V831
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (9 preceding siblings ...)
2020-12-12 5:12 ` [RFC PATCH 10/12] dt-bindings: spi: sun6i: add compatible for V831 SPI Icenowy Zheng
@ 2020-12-12 5:12 ` Icenowy Zheng
2020-12-14 14:39 ` Maxime Ripard
2020-12-12 5:13 ` [RFC PATCH 12/12] [DO NOT MERGE] ARM: dts: sun8i: v831: add a device tree file for Y20GA Icenowy Zheng
11 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 5:12 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng
V831 is a new chip by Allwinner, and its functionality is a subset of
V833 (another new chip with the same die but larger pin count).
Add a DTSI file for V831.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v831.dtsi | 244 ++++++++++++++++++++++++++++++
1 file changed, 244 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-v831.dtsi
diff --git a/arch/arm/boot/dts/sun8i-v831.dtsi b/arch/arm/boot/dts/sun8i-v831.dtsi
new file mode 100644
index 000000000000..7ddc4d33d8b2
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v831.dtsi
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-v833-ccu.h>
+#include <dt-bindings/reset/sun8i-v833-ccu.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&ccu CLK_CPUX>;
+ };
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun8i-v833-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun8i-v831-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x030090a0 0x20>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun8i-v831-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ spi0_qspi_pins: spi0-qspi-pins {
+ pins = "PC0", "PC2", "PC3", "PC4", "PC5";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi0_cs_pin: spi0-cs-pin {
+ pins = "PC1";
+ function = "spi0";
+ };
+
+ uart0_ph9_ph10_pins: uart0-ph9-ph10-pins {
+ pins = "PH9", "PH10";
+ function = "uart0";
+ };
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun8i-v831-mmc",
+ "allwinner,sun50i-a64-mmc";
+ reg = <0x04020000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun8i-v831-mmc",
+ "allwinner,sun50i-a64-mmc";
+ reg = <0x04021000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@5000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000000 0x400>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@5000400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000400 0x400>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@5000800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000800 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@5000c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000c00 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ spi0: spi@5010000 {
+ compatible = "allwinner,sun8i-v831-spi",
+ "allwinner,sun50i-h6-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x05010000 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@5011000 {
+ compatible = "allwinner,sun8i-v831-spi",
+ "allwinner,sun50i-h6-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x05011000 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ rtc: rtc@7000000 {
+ compatible = "allwinner,sun8i-v831-rtc";
+ reg = <0x07000000 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-output-names = "osc32k", "osc32k-out", "iosc";
+ #clock-cells = <1>;
+ };
+ };
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [RFC PATCH 12/12] [DO NOT MERGE] ARM: dts: sun8i: v831: add a device tree file for Y20GA
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
` (10 preceding siblings ...)
2020-12-12 5:12 ` [RFC PATCH 11/12] ARM: dts: sun8i: add DTSI file for V831 Icenowy Zheng
@ 2020-12-12 5:13 ` Icenowy Zheng
11 siblings, 0 replies; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-12 5:13 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec
Cc: devicetree, linux-arm-kernel, linux-kernel, Icenowy Zheng
Yi Y20GA is an IP camera with QG2101A chip (a rebranded Allwinner V831).
Add a device tree for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts | 53 +++++++++++++++++++++++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ce66ffd5a1bb..2b2e93bb9ee2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1212,7 +1212,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
- sun8i-v40-bananapi-m2-berry.dtb
+ sun8i-v40-bananapi-m2-berry.dtb \
+ sun8i-v831-yi-y20ga.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts b/arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
new file mode 100644
index 000000000000..16f4b6dbe0d2
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+#include "sun8i-v831.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Yi Camera Y20GA";
+ compatible = "xiaoyi,y20ga", "allwinner,sun8i-v831";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0_qspi_pins>, <&spi0_cs_pin>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph9_ph10_pins>;
+ status = "okay";
+};
--
2.28.0
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 06/12] dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC
2020-12-12 4:06 ` [RFC PATCH 06/12] dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC Icenowy Zheng
@ 2020-12-14 14:19 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-12-14 14:19 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, Maxime Ripard, linux-kernel, Alessandro Zummo,
linux-arm-kernel, Alexandre Belloni, linux-rtc, Chen-Yu Tsai,
Rob Herring, Jernej Skrabec
On Sat, 12 Dec 2020 12:06:35 +0800, Icenowy Zheng wrote:
> V831/V833 SoCs (the same die) have a RTC block similar to the one in H6,
> but allow to generate the osc32k clock from osc24M.
>
> Add a new compatible string for that.
>
> The functionality of dividing osc24M to generate osc32k is still TODO.
>
> Cc: Alessandro Zummo <a.zummo@towertech.it>
> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Cc: linux-rtc@vger.kernel.org
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> .../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml:102:13: [error] duplication of key "const" in mapping (key-duplicates)
dtschema/dtc warnings/errors:
make[1]: *** Deleting file 'Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.example.dts'
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 113, in get_single_data
return self.construct_document(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 123, in construct_document
for _dummy in generator:
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 723, in construct_yaml_map
value = self.construct_mapping(node)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 440, in construct_mapping
return BaseConstructor.construct_mapping(self, node, deep=deep)
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 257, in construct_mapping
if self.check_mapping_key(node, key_node, mapping, key, value):
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 295, in check_mapping_key
raise DuplicateKeyError(*args)
ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping
in "<unicode string>", line 101, column 13
found duplicate key "const" with value "allwinner,sun50i-h6-rtc" (original value: "allwinner,sun8i-v831-rtc")
in "<unicode string>", line 102, column 13
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [Documentation/devicetree/bindings/Makefile:59: Documentation/devicetree/bindings/processed-schema-examples.json] Error 123
make: *** [Makefile:1364: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1415362
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833
2020-12-12 4:04 ` [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833 Icenowy Zheng
@ 2020-12-14 14:21 ` Maxime Ripard
2020-12-14 15:19 ` Icenowy Zheng
2021-01-04 14:47 ` Linus Walleij
1 sibling, 1 reply; 25+ messages in thread
From: Maxime Ripard @ 2020-12-14 14:21 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, Jernej Skrabec, devicetree,
linux-arm-kernel, linux-kernel, Linus Walleij, linux-gpio
[-- Attachment #1: Type: text/plain, Size: 1408 bytes --]
On Sat, Dec 12, 2020 at 12:04:23PM +0800, Icenowy Zheng wrote:
> V831/V833 are new chips from Allwinner. They're the same die with
> different package.
>
> Add a pinctrl driver for them.
>
> The difference between V831/V833 pinctrl is implemented based on the
> user manual.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> drivers/pinctrl/sunxi/Kconfig | 5 +
> drivers/pinctrl/sunxi/Makefile | 1 +
> drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c | 743 +++++++++++++++++++++
> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
> 4 files changed, 751 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 593293584ecc..fc13335a3eda 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -73,6 +73,11 @@ config PINCTRL_SUN8I_V3S
> default MACH_SUN8I
> select PINCTRL_SUNXI
>
> +config PINCTRL_SUN8I_V83X
> + bool "Support for the Allwinner V831/V833 PIO"
> + default MACH_SUN8I
> + select PINCTRL_SUNXI
> +
We're not using the wildcard much, and I'd rather be consistent with the
name / Kconfig option scheme used for the clock driver (and the rest of
the SoCs in a similar situation)
Maxime
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 08/12] dt-bindings: mmc: sunxi: add compatible strings for V831 MMC
2020-12-12 5:03 ` [RFC PATCH 08/12] dt-bindings: mmc: sunxi: add compatible strings for V831 MMC Icenowy Zheng
@ 2020-12-14 14:38 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2020-12-14 14:38 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, Jernej Skrabec, devicetree,
linux-arm-kernel, linux-kernel, Ulf Hansson, linux-mmc
[-- Attachment #1: Type: text/plain, Size: 605 bytes --]
On Sat, Dec 12, 2020 at 01:03:42PM +0800, Icenowy Zheng wrote:
> V831 has MMC controllers similar to the ones on H6.
>
> Add a compatible string for them.
>
> The eMMC controller compatible is not added, because the eMMC controller
> is not available on V831, only V833.
>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Cc: linux-mmc@vger.kernel.org
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
There's pretty much the same comment than on the H616, it would be great
to not have any mode flags being set by the driver to avoid the mess we
have on the older SoCs right now.
Maxime
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 11/12] ARM: dts: sun8i: add DTSI file for V831
2020-12-12 5:12 ` [RFC PATCH 11/12] ARM: dts: sun8i: add DTSI file for V831 Icenowy Zheng
@ 2020-12-14 14:39 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2020-12-14 14:39 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, Jernej Skrabec, devicetree,
linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 280 bytes --]
On Sat, Dec 12, 2020 at 01:12:01PM +0800, Icenowy Zheng wrote:
> + spi0: spi@5010000 {
> + compatible = "allwinner,sun8i-v831-spi",
> + "allwinner,sun50i-h6-spi",
> + "allwinner,sun8i-h3-spi";
That's not the compatible you've documented in the binding
Maxime
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833
2020-12-14 14:21 ` Maxime Ripard
@ 2020-12-14 15:19 ` Icenowy Zheng
2020-12-14 16:42 ` Maxime Ripard
0 siblings, 1 reply; 25+ messages in thread
From: Icenowy Zheng @ 2020-12-14 15:19 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, Chen-Yu Tsai, Jernej Skrabec, devicetree,
linux-arm-kernel, linux-kernel, Linus Walleij, linux-gpio
于 2020年12月14日 GMT+08:00 下午10:21:18, Maxime Ripard <maxime@cerno.tech> 写到:
>On Sat, Dec 12, 2020 at 12:04:23PM +0800, Icenowy Zheng wrote:
>> V831/V833 are new chips from Allwinner. They're the same die with
>> different package.
>>
>> Add a pinctrl driver for them.
>>
>> The difference between V831/V833 pinctrl is implemented based on the
>> user manual.
>>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: linux-gpio@vger.kernel.org
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> drivers/pinctrl/sunxi/Kconfig | 5 +
>> drivers/pinctrl/sunxi/Makefile | 1 +
>> drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c | 743
>+++++++++++++++++++++
>> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
>> 4 files changed, 751 insertions(+)
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
>>
>> diff --git a/drivers/pinctrl/sunxi/Kconfig
>b/drivers/pinctrl/sunxi/Kconfig
>> index 593293584ecc..fc13335a3eda 100644
>> --- a/drivers/pinctrl/sunxi/Kconfig
>> +++ b/drivers/pinctrl/sunxi/Kconfig
>> @@ -73,6 +73,11 @@ config PINCTRL_SUN8I_V3S
>> default MACH_SUN8I
>> select PINCTRL_SUNXI
>>
>> +config PINCTRL_SUN8I_V83X
>> + bool "Support for the Allwinner V831/V833 PIO"
>> + default MACH_SUN8I
>> + select PINCTRL_SUNXI
>> +
>
>We're not using the wildcard much, and I'd rather be consistent with
>the
>name / Kconfig option scheme used for the clock driver (and the rest of
>the SoCs in a similar situation)
Well, call everything V831, or call everything V833, or call things usable
on V831 V831 and things only available to V833 V833?
>
>Maxime
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833
2020-12-14 15:19 ` Icenowy Zheng
@ 2020-12-14 16:42 ` Maxime Ripard
0 siblings, 0 replies; 25+ messages in thread
From: Maxime Ripard @ 2020-12-14 16:42 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, Jernej Skrabec, devicetree,
linux-arm-kernel, linux-kernel, Linus Walleij, linux-gpio
[-- Attachment #1: Type: text/plain, Size: 1946 bytes --]
On Mon, Dec 14, 2020 at 11:19:48PM +0800, Icenowy Zheng wrote:
>
>
> 于 2020年12月14日 GMT+08:00 下午10:21:18, Maxime Ripard <maxime@cerno.tech> 写到:
> >On Sat, Dec 12, 2020 at 12:04:23PM +0800, Icenowy Zheng wrote:
> >> V831/V833 are new chips from Allwinner. They're the same die with
> >> different package.
> >>
> >> Add a pinctrl driver for them.
> >>
> >> The difference between V831/V833 pinctrl is implemented based on the
> >> user manual.
> >>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: linux-gpio@vger.kernel.org
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> ---
> >> drivers/pinctrl/sunxi/Kconfig | 5 +
> >> drivers/pinctrl/sunxi/Makefile | 1 +
> >> drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c | 743
> >+++++++++++++++++++++
> >> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
> >> 4 files changed, 751 insertions(+)
> >> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
> >>
> >> diff --git a/drivers/pinctrl/sunxi/Kconfig
> >b/drivers/pinctrl/sunxi/Kconfig
> >> index 593293584ecc..fc13335a3eda 100644
> >> --- a/drivers/pinctrl/sunxi/Kconfig
> >> +++ b/drivers/pinctrl/sunxi/Kconfig
> >> @@ -73,6 +73,11 @@ config PINCTRL_SUN8I_V3S
> >> default MACH_SUN8I
> >> select PINCTRL_SUNXI
> >>
> >> +config PINCTRL_SUN8I_V83X
> >> + bool "Support for the Allwinner V831/V833 PIO"
> >> + default MACH_SUN8I
> >> + select PINCTRL_SUNXI
> >> +
> >
> >We're not using the wildcard much, and I'd rather be consistent with
> >the
> >name / Kconfig option scheme used for the clock driver (and the rest of
> >the SoCs in a similar situation)
>
> Well, call everything V831, or call everything V833, or call things usable
> on V831 V831 and things only available to V833 V833?
It would feel more natural to have everything called v831, with things
v833-specific obviously called v833
Maxime
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 01/12] dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU
2020-12-12 4:01 ` [RFC PATCH 01/12] dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU Icenowy Zheng
@ 2020-12-15 16:16 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-12-15 16:16 UTC (permalink / raw)
To: Icenowy Zheng
Cc: devicetree, Maxime Ripard, Rob Herring, linux-arm-kernel,
linux-kernel, Jernej Skrabec, Chen-Yu Tsai
On Sat, 12 Dec 2020 12:01:57 +0800, Icenowy Zheng wrote:
> V831/V833 has a CCU similar to the ones on H6/A100.
>
> Add a compatible string for it.
>
> As the user manual do not mention the difference between V831 and V833
> in the CCU chapter, only a single compatible string for V833
> (full-functional chip) is made.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 02/12] dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers
2020-12-12 4:03 ` [RFC PATCH 02/12] dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers Icenowy Zheng
@ 2020-12-15 16:18 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-12-15 16:18 UTC (permalink / raw)
To: Icenowy Zheng
Cc: linux-arm-kernel, Jernej Skrabec, devicetree, Chen-Yu Tsai,
linux-kernel, Rob Herring, Maxime Ripard
On Sat, 12 Dec 2020 12:03:08 +0800, Icenowy Zheng wrote:
> As the device tree needs the clock/reset indices, add them to DT binding
> headers.
>
> The driver itself will be then added.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> include/dt-bindings/clock/sun8i-v833-ccu.h | 89 ++++++++++++++++++++++
> include/dt-bindings/reset/sun8i-v833-ccu.h | 52 +++++++++++++
> 2 files changed, 141 insertions(+)
> create mode 100644 include/dt-bindings/clock/sun8i-v833-ccu.h
> create mode 100644 include/dt-bindings/reset/sun8i-v833-ccu.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 04/12] dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl
2020-12-12 4:04 ` [RFC PATCH 04/12] dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl Icenowy Zheng
@ 2020-12-15 16:18 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-12-15 16:18 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Linus Walleij, Chen-Yu Tsai, linux-kernel,
linux-gpio, Jernej Skrabec, Maxime Ripard, linux-arm-kernel,
devicetree
On Sat, 12 Dec 2020 12:04:22 +0800, Icenowy Zheng wrote:
> V831/V833 are a pair of new Allwinner chips. The difference between them
> is similar to V3s/V3, but the chip design is similar to newer Allwinner
> chips started from H6.
>
> Add compatible strings for V831/V833 pinctrl.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 09/12] dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT
2020-12-12 5:05 ` [RFC PATCH 09/12] dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT Icenowy Zheng
@ 2020-12-15 16:27 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-12-15 16:27 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec, devicetree,
linux-arm-kernel, linux-kernel, Wim Van Sebroeck, Guenter Roeck,
linux-watchdog
On Sat, Dec 12, 2020 at 01:05:16PM +0800, Icenowy Zheng wrote:
> V831/V833 has a watchdog similar to the ones on previous Allwinner SoCs
> after sun6i.
>
> Add a compatible string for it.
>
> Cc: Wim Van Sebroeck <wim@linux-watchdog.org>
> Cc: Guenter Roeck <linux@roeck-us.net>
> Cc: linux-watchdog@vger.kernel.org
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +++
> 1 file changed, 3 insertions(+)
This is going to conflict with Andre's series for H616.
>
> diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
> index e8f226376108..2f3c350b0057 100644
> --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
> +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
> @@ -18,6 +18,9 @@ properties:
> oneOf:
> - const: allwinner,sun4i-a10-wdt
> - const: allwinner,sun6i-a31-wdt
> + - items:
> + - const: allwinner,sun8i-v831-wdt
> + - const: allwinner,sun6i-a31-wdt
> - items:
> - const: allwinner,sun50i-a64-wdt
> - const: allwinner,sun6i-a31-wdt
> --
> 2.28.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 10/12] dt-bindings: spi: sun6i: add compatible for V831 SPI
2020-12-12 5:12 ` [RFC PATCH 10/12] dt-bindings: spi: sun6i: add compatible for V831 SPI Icenowy Zheng
@ 2020-12-15 16:32 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2020-12-15 16:32 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec, devicetree,
linux-arm-kernel, linux-kernel, Mark Brown, linux-spi
On Sat, Dec 12, 2020 at 01:12:00PM +0800, Icenowy Zheng wrote:
> V831 has a SPI controller similar to the H6 one.
>
> Add a compatible string for it.
>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: linux-spi@vger.kernel.org
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> H6 and V831 SPI controllers is not totally the same with H3: they have
> QSPI support added. Here V831 compatible string is just added in
> parallel with H6 one, but maybe we should make H6 SPI do not fallback to
> H3 one, and add H6 one as fallback to V831?
A fallback is really only needed if there's a user you expect to work
unmodified. For example, say a new DMA mode is added, but that's
something a bootloader wouldn't use. Given QSPI mode is probably
fundamentally different?, then a fallback is probably not needed.
>
> .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
> index 7866a655d81c..a620ff30033e 100644
> --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
> @@ -24,6 +24,7 @@ properties:
> - items:
> - enum:
> - allwinner,sun8i-r40-spi
> + - allwinner,sun8i-v831-spi
> - allwinner,sun50i-h6-spi
> - const: allwinner,sun8i-h3-spi
>
> --
> 2.28.0
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833
2020-12-12 4:04 ` [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833 Icenowy Zheng
2020-12-14 14:21 ` Maxime Ripard
@ 2021-01-04 14:47 ` Linus Walleij
1 sibling, 0 replies; 25+ messages in thread
From: Linus Walleij @ 2021-01-04 14:47 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Jernej Skrabec,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel, open list:GPIO SUBSYSTEM
Hi Icenowy,
On Sat, Dec 12, 2020 at 5:04 AM Icenowy Zheng <icenowy@aosc.io> wrote:
> V831/V833 are new chips from Allwinner. They're the same die with
> different package.
>
> Add a pinctrl driver for them.
>
> The difference between V831/V833 pinctrl is implemented based on the
> user manual.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Could you respin patches 4 & 5 with Maxime's comments
addressed and include Rob's ACK on patch 4? Also please rebase on v5.11-rc1.
I suppose these two patches are independent from the rest of the stuff
in the series so it can be managed separately?
Yours.
Linus Walleij
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2021-01-04 14:49 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-12 4:01 [RFC PATCH 00/12] Support for Allwinner V831 SoC Icenowy Zheng
2020-12-12 4:01 ` [RFC PATCH 01/12] dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU Icenowy Zheng
2020-12-15 16:16 ` Rob Herring
2020-12-12 4:03 ` [RFC PATCH 02/12] dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers Icenowy Zheng
2020-12-15 16:18 ` Rob Herring
2020-12-12 4:03 ` [RFC PATCH 03/12] clk: sunxi-ng: add CCU driver for V831/V833 Icenowy Zheng
2020-12-12 4:04 ` [RFC PATCH 04/12] dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl Icenowy Zheng
2020-12-15 16:18 ` Rob Herring
2020-12-12 4:04 ` [RFC PATCH 05/12] pinctrl: sunxi: add pinctrl driver for V831/V833 Icenowy Zheng
2020-12-14 14:21 ` Maxime Ripard
2020-12-14 15:19 ` Icenowy Zheng
2020-12-14 16:42 ` Maxime Ripard
2021-01-04 14:47 ` Linus Walleij
2020-12-12 4:06 ` [RFC PATCH 06/12] dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC Icenowy Zheng
2020-12-14 14:19 ` Rob Herring
2020-12-12 4:09 ` [RFC PATCH 07/12] " Icenowy Zheng
2020-12-12 5:03 ` [RFC PATCH 08/12] dt-bindings: mmc: sunxi: add compatible strings for V831 MMC Icenowy Zheng
2020-12-14 14:38 ` Maxime Ripard
2020-12-12 5:05 ` [RFC PATCH 09/12] dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT Icenowy Zheng
2020-12-15 16:27 ` Rob Herring
2020-12-12 5:12 ` [RFC PATCH 10/12] dt-bindings: spi: sun6i: add compatible for V831 SPI Icenowy Zheng
2020-12-15 16:32 ` Rob Herring
2020-12-12 5:12 ` [RFC PATCH 11/12] ARM: dts: sun8i: add DTSI file for V831 Icenowy Zheng
2020-12-14 14:39 ` Maxime Ripard
2020-12-12 5:13 ` [RFC PATCH 12/12] [DO NOT MERGE] ARM: dts: sun8i: v831: add a device tree file for Y20GA Icenowy Zheng
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