From: Dongjiu Geng <gengdongjiu@huawei.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh+dt@kernel.org>, <vkoul@kernel.org>,
<dan.j.williams@intel.com>, <p.zabel@pengutronix.de>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <dmaengine@vger.kernel.org>,
<gengdongjiu@huawei.com>
Subject: [PATCH v6 3/4] dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller
Date: Sat, 12 Dec 2020 13:05:57 +0000 [thread overview]
Message-ID: <20201212130558.49086-4-gengdongjiu@huawei.com> (raw)
In-Reply-To: <20201212130558.49086-1-gengdongjiu@huawei.com>
The Hiedma Controller v310 Provides eight DMA channels, each
channel can be configured for one-way transfer. The data can
be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
documentation describes DT bindings of this controller.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
.../bindings/dma/hisilicon,hiedmacv310.yaml | 94 +++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml
diff --git a/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml
new file mode 100644
index 000000000000..f57703fbbe7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/hisilicon,hiedmacv310.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Hiedma Controller v310 Device Tree Bindings
+
+description: |
+ These bindings describe the DMA engine included in the HiSilicon Hiedma
+ Controller v310 Device.
+
+maintainers:
+ - Dongjiu Geng <gengdongjiu@huawei.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ const: 2
+
+ compatible:
+ const: hisilicon,hiedmacv310
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ hisi,misc-control:
+ $ref: /schemas/types.yaml#definitions/phandle-array
+ description: phandle pointing to the misc controller provider node and base register.
+
+ clocks:
+ items:
+ - description: apb clock
+ - description: axi clock
+
+ clock-names:
+ items:
+ - const: apb_pclk
+ - const: axi_aclk
+
+ resets:
+ description: phandle pointing to the dma reset controller provider node.
+
+ reset-names:
+ items:
+ - const: dma-reset
+
+ dma-requests:
+ maximum: 32
+
+ dma-channels:
+ maximum: 8
+
+
+required:
+ - "#dma-cells"
+ - compatible
+ - hisi,misc-control
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - dma-requests
+ - dma-channels
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/hi3559av100-clock.h>
+
+ dma: dma-controller@10040000 {
+ compatible = "hisilicon,hiedmacv310";
+ reg = <0x10040000 0x1000>;
+ hisi,misc-control = <&misc_ctrl 0x144>;
+ interrupts = <0 82 4>;
+ clocks = <&clock HI3559AV100_EDMAC1_CLK>, <&clock HI3559AV100_EDMAC1_AXICLK>;
+ clock-names = "apb_pclk", "axi_aclk";
+ resets = <&clock 0x16c 7>;
+ reset-names = "dma-reset";
+ dma-requests = <32>;
+ dma-channels = <8>;
+ #dma-cells = <2>;
+ };
+
+...
--
2.17.1
next prev parent reply other threads:[~2020-12-11 11:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-12 13:05 [PATCH v6 0/4] Enable Hi3559A SOC clock and HiSilicon Hiedma Controller Dongjiu Geng
2020-12-12 13:05 ` [PATCH v6 1/4] dt-bindings: Document the hi3559a clock bindings Dongjiu Geng
2020-12-12 13:05 ` [PATCH v6 2/4] clk: hisilicon: Add clock driver for hi3559A SoC Dongjiu Geng
2020-12-12 13:05 ` Dongjiu Geng [this message]
2020-12-12 13:05 ` [PATCH v6 4/4] dmaengine: dma: Add Hiedma Controller v310 Device Driver Dongjiu Geng
2020-12-12 13:08 [PATCH v6 0/4] Enable Hi3559A SOC clock and HiSilicon Hiedma Controller Dongjiu Geng
2020-12-12 13:08 ` [PATCH v6 3/4] dt: bindings: dma: Add DT bindings for " Dongjiu Geng
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