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From: Lorenzo Stoakes <>
To: Dave Hansen <>,
	Andy Lutomirski <>,
	Peter Zijlstra <>,
	Thomas Gleixner <>,
	Ingo Molnar <>, Borislav Petkov <>,, "H . Peter Anvin" <>
Cc:, Lorenzo Stoakes <>
Subject: [PATCH] x86/mm: increase pgt_buf size for 5-level page tables
Date: Tue, 15 Dec 2020 20:56:41 +0000	[thread overview]
Message-ID: <> (raw)

pgt_buf is used to allocate page tables on initial direct page mapping
bootstrapping us into being able to allocate these before the direct
mapping makes further pages available.

INIT_PGD_PAGE_COUNT is set to 6 pages (doubled for KASLR) - 3 (PUD, PMD,
PTE) for the 1 MiB ISA mapping and 3 more for the first direct mapping
assignment in each case providing 2 MiB of address space.

This has not been updated for 5-level page tables which additionally has a
P4D page table level above PUD.

In most instances this will not have a material impact as the first 4 page
levels allocated for the ISA mapping will provide sufficient address space
to encompass all further address mappings. If the first direct mapping is
within 512 GiB of the ISA mapping we need only add a PMD and PTE in the
instance where we are using 4 KiB page tables (e.g. CONFIG_DEBUG_PAGEALLOC
is enabled) and only a PMD if we can use 2 MiB pages (the first allocation
is limited to PMD_SIZE so we can't use a GiB page there).

However if we have more than 512 GiB of RAM and are allocating 4 KiB page
size we require 3 further page tables and if we have more than 256 TiB of
RAM at 4 KiB or 2 MiB page size we require a further 3 or 4 page tables

This patch updates INIT_PGD_PAGE_COUNT to reflect this.

Signed-off-by: Lorenzo Stoakes <>
 arch/x86/mm/init.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index e26f5c5c6565..0ee7dc9a5a65 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -157,16 +157,25 @@ __ref void *alloc_low_pages(unsigned int num)
- * By default need 3 4k for initial PMD_SIZE,  3 4k for 0-ISA_END_ADDRESS.
- * With KASLR memory randomization, depending on the machine e820 memory
- * and the PUD alignment. We may need twice more pages when KASLR memory
+ * By default we need to be able to allocate page tables below PGD firstly for
+ * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping.
+ * With KASLR memory randomization, depending on the machine e820 memory and the
+ * PUD alignment, we may need twice that many pages when KASLR memory
  * randomization is enabled.
+#ifndef CONFIG_X86_5LEVEL
+#define INIT_PGD_PAGE_TABLES    3
+#define INIT_PGD_PAGE_TABLES    4
-#define INIT_PGD_PAGE_COUNT      6
-#define INIT_PGD_PAGE_COUNT      12
 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
 void  __init early_alloc_pgt_buf(void)

             reply	other threads:[~2020-12-15 20:57 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-15 20:56 Lorenzo Stoakes [this message]
2020-12-16 10:56 ` [PATCH] x86/mm: increase pgt_buf size for 5-level page tables Kirill A. Shutemov
2020-12-16 18:04 ` Dave Hansen
2021-01-04 14:52   ` Lorenzo Stoakes
2021-01-04 18:29 ` [tip: x86/mm] x86/mm: Increase " tip-bot2 for Lorenzo Stoakes

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