From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FB55C1B0D8 for ; Thu, 17 Dec 2020 00:39:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 24CC223787 for ; Thu, 17 Dec 2020 00:39:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727808AbgLQAjS (ORCPT ); Wed, 16 Dec 2020 19:39:18 -0500 Received: from mga03.intel.com ([134.134.136.65]:41740 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727126AbgLQAjS (ORCPT ); Wed, 16 Dec 2020 19:39:18 -0500 IronPort-SDR: XGMrxkwFhYQpZI6EHZkhVsJOQMmV0Sw2gq+cPR67QzZ8iYbJ3cdR5tRVSZ3N6yepNaMrVuAKMv KYkv8gBXHyFg== X-IronPort-AV: E=McAfee;i="6000,8403,9837"; a="175266136" X-IronPort-AV: E=Sophos;i="5.78,425,1599548400"; d="scan'208";a="175266136" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2020 16:38:36 -0800 IronPort-SDR: NimDuO3JSSCaVpcE48OB6QWQniCI0fiXPNzekJI5l7NmE3AKdZihNJaKV633ov9z2pi3EL+dvK tZn+LkRliH4A== X-IronPort-AV: E=Sophos;i="5.78,425,1599548400"; d="scan'208";a="369434314" Received: from iweiny-desk2.sc.intel.com (HELO localhost) ([10.3.52.147]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2020 16:38:36 -0800 Date: Wed, 16 Dec 2020 16:38:36 -0800 From: Ira Weiny To: Andy Lutomirski Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Peter Zijlstra , Dave Hansen , X86 ML , LKML , Andrew Morton , Fenghua Yu , "open list:DOCUMENTATION" , linux-nvdimm , Linux-MM , "open list:KERNEL SELFTEST FRAMEWORK" , Dan Williams , Greg KH Subject: Re: [PATCH V3.1] entry: Pass irqentry_state_t by reference Message-ID: <20201217003835.GZ1563847@iweiny-DESK2.sc.intel.com> References: <20201106232908.364581-6-ira.weiny@intel.com> <20201124060956.1405768-1-ira.weiny@intel.com> <20201216013202.GY1563847@iweiny-DESK2.sc.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.11.1 (2018-12-01) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Dec 15, 2020 at 06:09:02PM -0800, Andy Lutomirski wrote: > On Tue, Dec 15, 2020 at 5:32 PM Ira Weiny wrote: > > > > On Fri, Dec 11, 2020 at 02:14:28PM -0800, Andy Lutomirski wrote: > > > On Mon, Nov 23, 2020 at 10:10 PM wrote: > > > > IOW we have: > > > > > > struct extended_pt_regs { > > > bool rcu_whatever; > > > other generic fields here; > > > struct arch_extended_pt_regs arch_regs; > > > struct pt_regs regs; > > > }; > > > > > > and arch_extended_pt_regs has unsigned long pks; > > > > > > and instead of passing a pointer to irqentry_state_t to the generic > > > entry/exit code, we just pass a pt_regs pointer. And we have a little > > > accessor like: > > > > > > struct extended_pt_regs *extended_regs(struct pt_regs *) { return > > > container_of(...); } > > > > > > And we tell eBPF that extended_pt_regs is NOT ABI, and we will change > > > it whenever we feel like just to keep you on your toes, thank you very > > > much. > > > > > > Does this seem reasonable? > > > > Conceptually yes. But I'm failing to see how this implementation can be made > > generic for the generic fields. The pks fields, assuming they stay x86 > > specific, would be reasonable to add in PUSH_AND_CLEAR_REGS. But the > > rcu/lockdep field is generic. Wouldn't we have to modify every architecture to > > add space for the rcu/lockdep bool? > > > > If not, where is a generic place that could be done? Basically I'm missing how > > the effective stack structure can look like this: > > > > > struct extended_pt_regs { > > > bool rcu_whatever; > > > other generic fields here; > > > struct arch_extended_pt_regs arch_regs; > > > struct pt_regs regs; > > > }; > > > > It seems more reasonable to make it look like: > > > > #ifdef CONFIG_ARCH_HAS_SUPERVISOR_PKEYS > > struct extended_pt_regs { > > unsigned long pkrs; > > struct pt_regs regs; > > }; > > #endif > > > > And leave the rcu/lockdep bool passed by value as before (still in C). > > We could certainly do this, I'm going to start with this basic support. Because I have 0 experience in most of these architectures. > but we could also allocate some generic > space. PUSH_AND_CLEAR_REGS would get an extra instruction like: > > subq %rsp, $GENERIC_PTREGS_SIZE > > or however this should be written. That field would be defined in > asm-offsets.c. And yes, all the generic-entry architectures would > need to get onboard. What do you mean by 'generic-entry' architectures? I thought they all used the generic entry code? Regardless I would need to start another thread on this topic with any of those architecture maintainers to see what the work load would be for this. I don't think I can do it on my own. FWIW I think it is a bit unfair to hold up the PKS support in x86 for making these generic fields part of the stack frame. So perhaps that could be made a follow on to the PKS series? > > If we wanted to be fancy, we could split the generic area into > initialize-to-zero and uninitialized for debugging purposes, but that > might be more complication than is worthwhile. Ok, agreed, but this is step 3 or 4 at the earliest. Ira