From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1234FC3526F for ; Fri, 18 Dec 2020 20:56:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E8DFE23DB3 for ; Fri, 18 Dec 2020 20:56:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726207AbgLRUzr (ORCPT ); Fri, 18 Dec 2020 15:55:47 -0500 Received: from leonov.paulk.fr ([185.233.101.22]:42878 "EHLO leonov.paulk.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725775AbgLRUzq (ORCPT ); Fri, 18 Dec 2020 15:55:46 -0500 Received: from gagarine.paulk.fr (gagarine [192.168.1.127]) by leonov.paulk.fr (Postfix) with ESMTPS id E5A6EBFDE9; Fri, 18 Dec 2020 21:55:03 +0100 (CET) Received: by gagarine.paulk.fr (Postfix, from userid 114) id 58D14C1D27; Fri, 18 Dec 2020 21:55:03 +0100 (CET) Received: from localhost.localdomain (collins [192.168.1.129]) by gagarine.paulk.fr (Postfix) with ESMTP id 4F57AC1D23; Fri, 18 Dec 2020 21:54:38 +0100 (CET) From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Paul Kocialkowski Subject: [PATCH v2 2/2] ARM: dts: sun8i-v3s: Add PWM controller and pins definitions Date: Fri, 18 Dec 2020 21:54:36 +0100 Message-Id: <20201218205436.2326872-2-contact@paulk.fr> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201218205436.2326872-1-contact@paulk.fr> References: <20201218205436.2326872-1-contact@paulk.fr> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This introduces definitions for the PWM controller found in the V3s, as well as associated pins. This fashion of the controller has two PWM outputs and is register-compatible with the A20. Both PWM outputs were tested on a Lichee Pi Zero with a simple transistor-LED setup. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index bff822b9fa01..f02aa988156d 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -404,6 +404,16 @@ spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; }; + + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; }; timer@1c20c00 { @@ -422,6 +432,15 @@ wdt0: watchdog@1c20ca0 { clocks = <&osc24M>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-v3s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x400>; -- 2.29.2