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[84.226.167.205]) by smtp.googlemail.com with ESMTPSA id pk19sm6666596ejb.32.2020.12.19.02.57.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Dec 2020 02:57:22 -0800 (PST) Date: Sat, 19 Dec 2020 11:57:20 +0100 From: Krzysztof Kozlowski To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Mark Brown , Liam Girdwood , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Peter Geis , Nicolas Chauvet , "Rafael J. Wysocki" , Kevin Hilman , Peter De Schrijver , Viresh Kumar , Stephen Boyd , Michael Turquette , devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v2 07/48] dt-bindings: arm: tegra: Add binding for core power domain Message-ID: <20201219105720.GA5323@kozik-lap> References: <20201217180638.22748-1-digetx@gmail.com> <20201217180638.22748-8-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201217180638.22748-8-digetx@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Dec 17, 2020 at 09:05:57PM +0300, Dmitry Osipenko wrote: > All NVIDIA Tegra SoCs have a core power domain where majority of hardware > blocks reside. Add binding for the core power domain. > > Signed-off-by: Dmitry Osipenko > --- > .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > new file mode 100644 > index 000000000000..f3d8fd2d8371 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-core-domain.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra Core Power Domain > + > +maintainers: > + - Dmitry Osipenko > + - Jon Hunter > + - Thierry Reding > + > +properties: > + compatible: > + enum: > + - nvidia,tegra20-core-domain > + - nvidia,tegra30-core-domain The file should be in bindings/power. Include also the power-domain.yaml schema. > + > + operating-points-v2: > + description: > + Should contain level, voltages and opp-supported-hw property. > + The supported-hw is a bitfield indicating SoC speedo or process > + ID mask. > + > + "#power-domain-cells": > + const: 0 > + > + power-supply: > + description: > + Phandle to voltage regulator connected to the SoC Core power rail. > + > +required: > + - compatible > + - operating-points-v2 > + - "#power-domain-cells" > + - power-supply > + > +additionalProperties: false > + > +examples: > + - | > + core-domain { power-domain (to follow schema and devicetree spec) Best regards, Krzysztof > + compatible = "nvidia,tegra20-core-domain"; > + operating-points-v2 = <&opp_table>; > + power-supply = <®ulator>; > + #power-domain-cells = <0>; > + }; > -- > 2.29.2 >