From: "Pali Rohár" <pali@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>,
Marek Behun <marek.behun@nic.cz>,
Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Terry Zhou <bjzhou@marvell.com>,
Konstantin Porotchkin <kostap@marvell.com>
Subject: Re: [PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
Date: Sun, 20 Dec 2020 17:21:35 +0100 [thread overview]
Message-ID: <20201220162135.yyijnczu6dxgnpda@pali> (raw)
In-Reply-To: <160842189035.1580929.16863503861561557281@swboyd.mtv.corp.google.com>
On Saturday 19 December 2020 15:51:30 Stephen Boyd wrote:
> Quoting Pali Rohár (2020-11-06 02:00:39)
> > From: Terry Zhou <bjzhou@marvell.com>
> >
> > There is an error in the current code that the XTAL MODE
> > pin was set to NB MPP1_31 which should be NB MPP1_9.
> > The latch register of NB MPP1_9 has different offset of 0x8.
> >
> > Signed-off-by: Terry Zhou <bjzhou@marvell.com>
> > [pali: Fix pin name in commit message]
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
> > Cc: stable@vger.kernel.org
> >
> > ---
>
> Applied to clk-next
Hello Stephen! As this is fix also for stable releases, could you please
queue this patch for 5.11 release?
next prev parent reply other threads:[~2020-12-20 16:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-06 10:00 [PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 Pali Rohár
2020-11-06 10:51 ` Marek Behún
2020-11-13 10:19 ` Pali Rohár
2020-12-01 9:46 ` Pali Rohár
2020-12-19 23:51 ` Stephen Boyd
2020-12-20 16:21 ` Pali Rohár [this message]
2020-12-21 1:47 ` Stephen Boyd
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