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From: "Chia-Wei, Wang" <chiawei_wang@aspeedtech.com>
To: <lee.jones@linaro.org>, <robh+dt@kernel.org>, <joel@jms.id.au>,
	<andrew@aj.id.au>, <linus.walleij@linaro.org>, <minyard@acm.org>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
	<openbmc@lists.ozlabs.org>
Cc: <BMC-SW@aspeedtech.com>, <haiyue.wang@linux.intel.com>,
	<cyrilbur@gmail.com>, <rlippert@google.com>
Subject: [PATCH v3 0/5] Remove LPC register partitioning
Date: Mon, 21 Dec 2020 13:56:18 +0800	[thread overview]
Message-ID: <20201221055623.31463-1-chiawei_wang@aspeedtech.com> (raw)

The LPC controller has no concept of the BMC and the Host partitions.
The incorrect partitioning can impose unnecessary range restrictions
on register access through the syscon regmap interface.

For instance, HICRB contains the I/O port address configuration
of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access
HICRB as it is located at the other LPC partition.

In addition, to be backward compatible, the newly added HW control
bits could be located at any reserved bits over the LPC addressing
space.

Thereby, this patch series aims to remove the LPC partitioning for
better driver development and maintenance. This requires the change
to both the device tree and the driver implementation. To ensure
both sides are synchronously updated, a v2 binding check is added.

Changes since v2:
	- Add v2 binding check to ensure the synchronization between the
	  device tree change and the driver register offset fix.

Changes since v1:
	- Add the fix to the aspeed-lpc binding documentation.

Chia-Wei, Wang (5):
  dt-bindings: aspeed-lpc: Remove LPC partitioning
  ARM: dts: Remove LPC BMC and Host partitions
  ipmi: kcs: aspeed: Adapt to new LPC DTS layout
  pinctrl: aspeed-g5: Adapt to new LPC device tree layout
  soc: aspeed: Adapt to new LPC device tree layout

 .../devicetree/bindings/mfd/aspeed-lpc.txt    |  99 +++----------
 arch/arm/boot/dts/aspeed-g4.dtsi              |  74 ++++------
 arch/arm/boot/dts/aspeed-g5.dtsi              | 135 ++++++++----------
 arch/arm/boot/dts/aspeed-g6.dtsi              | 135 ++++++++----------
 drivers/char/ipmi/kcs_bmc_aspeed.c            |  35 +++--
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c    |  19 ++-
 drivers/soc/aspeed/aspeed-lpc-ctrl.c          |  20 ++-
 drivers/soc/aspeed/aspeed-lpc-snoop.c         |  23 +--
 8 files changed, 232 insertions(+), 308 deletions(-)

-- 
2.17.1


             reply	other threads:[~2020-12-21  5:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-21  5:56 Chia-Wei, Wang [this message]
2020-12-21  5:56 ` [PATCH v3 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning Chia-Wei, Wang
2020-12-21  5:56 ` [PATCH v3 2/5] ARM: dts: Remove LPC BMC and Host partitions Chia-Wei, Wang
2020-12-21  5:56 ` [PATCH v3 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout Chia-Wei, Wang
2020-12-21  7:53   ` Haiyue Wang
2020-12-21  7:59     ` Haiyue Wang
2020-12-22  2:13       ` ChiaWei Wang
2020-12-21  5:56 ` [PATCH v3 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout Chia-Wei, Wang
2020-12-21  5:56 ` [PATCH v3 5/5] soc: aspeed: " Chia-Wei, Wang
2021-01-04 15:30 ` [PATCH v3 0/5] Remove LPC register partitioning Jonathan Cameron

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