From: Roger Lu <roger.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Enric Balletbo Serra <eballetbo@gmail.com>,
Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: Fan Chen <fan.chen@mediatek.com>,
HenryC Chen <HenryC.Chen@mediatek.com>,
YT Lee <yt.lee@mediatek.com>,
Xiaoqing Liu <Xiaoqing.Liu@mediatek.com>,
Charles Yang <Charles.Yang@mediatek.com>,
Angus Lin <Angus.Lin@mediatek.com>,
Mark Rutland <mark.rutland@arm.com>, Nishanth Menon <nm@ti.com>,
Roger Lu <roger.lu@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>
Subject: [PATCH v10 2/7] [v10,2/7]: arm64: dts: mt8183: add svs device information
Date: Sun, 27 Dec 2020 18:54:44 +0800 [thread overview]
Message-ID: <20201227105449.11452-3-roger.lu@mediatek.com> (raw)
In-Reply-To: <20201227105449.11452-1-roger.lu@mediatek.com>
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 9cfd961c45eb..b017eb7fbf2a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -479,6 +479,18 @@
status = "disabled";
};
+ svs: svs@1100b000 {
+ compatible = "mediatek,mt8183-svs";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calibration>,
+ <&thermal_calibration>;
+ nvmem-cell-names = "svs-calibration-data",
+ "t-calibration-data";
+ };
+
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8183-i2c";
reg = <0 0x1100f000 0 0x1000>,
@@ -724,6 +736,14 @@
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x11f10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
+ svs_calibration: calib@580 {
+ reg = <0x580 0x64>;
+ };
};
u3phy: usb-phy@11f40000 {
--
2.18.0
next prev parent reply other threads:[~2020-12-27 10:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-27 10:54 [PATCH v10 0/7] soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2020-12-27 10:54 ` [PATCH v10 1/7] [v10,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings Roger Lu
2020-12-27 16:56 ` [PATCH v10 1/7] [v10, 1/7]: " Rob Herring
2020-12-31 18:12 ` [PATCH v10 1/7] [v10,1/7]: " Rob Herring
2020-12-27 10:54 ` Roger Lu [this message]
2020-12-27 10:54 ` [PATCH v10 3/7] [v10,3/7]: soc: mediatek: SVS: introduce MTK SVS engine Roger Lu
2020-12-31 2:10 ` [PATCH v10 3/7] [v10, 3/7]: " Nicolas Boichat
2021-01-04 8:51 ` Roger Lu
2021-01-04 9:27 ` Nicolas Boichat
2021-01-04 9:52 ` Roger Lu
2021-01-06 8:41 ` Roger Lu
2021-01-06 8:44 ` Nicolas Boichat
2020-12-27 10:54 ` [PATCH v10 4/7] [v10,4/7]: soc: mediatek: SVS: add debug commands Roger Lu
2020-12-27 10:54 ` [PATCH v10 5/7] [v10,5/7]: dt-bindings: soc: mediatek: add mt8192 svs dt-bindings Roger Lu
2020-12-27 10:54 ` [PATCH v10 6/7] [v10,6/7]: arm64: dts: mt8192: add svs device information Roger Lu
2020-12-27 10:54 ` [PATCH v10 7/7] [v10,7/7]: soc: mediatek: SVS: add mt8192 SVS GPU driver Roger Lu
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