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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: linux-mips@vger.kernel.org
Cc: "Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
	"WANG Xuerui" <git@xen0n.name>,
	"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
	"Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
	"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
	"Paul Cercueil" <paul@crapouillou.net>,
	"Tiezhu Yang" <yangtiezhu@loongson.cn>,
	"Huacai Chen" <chenhc@lemote.com>, "YunQiang Su" <syq@debian.org>,
	"Liangliang Huang" <huanglllzu@gmail.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] MIPS: cpu-probe: Vulnerabilities for Loongson cores
Date: Wed, 30 Dec 2020 11:23:09 +0800	[thread overview]
Message-ID: <20201230032314.10042-3-jiaxun.yang@flygoat.com> (raw)
In-Reply-To: <20201230032314.10042-1-jiaxun.yang@flygoat.com>

Loongson64C is known to be vulnerable to meltdown according to
PoC from Rui Wang <r@hev.cc>.

Loongson64G defended these side-channel attack by silicon.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/kernel/cpu-probe.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 2460783dbdb1..24b21f51353c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2092,6 +2092,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
 		c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
 			MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
 		c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
+		c->vulnerabilities |= MIPS_VULNBL_MELTDOWN;
+		c->vulnerable |= MIPS_VULNBL_MELTDOWN;
 		break;
 	case PRID_IMP_LOONGSON_64G:
 		c->cputype = CPU_LOONGSON64;
@@ -2100,6 +2102,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
 		set_isa(c, MIPS_CPU_ISA_M64R2);
 		decode_cpucfg(c);
 		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+		c->vulnerabilities |= MIPS_VULNBL_MELTDOWN |
+			      MIPS_VULNBL_SPECTRE_V1 | MIPS_VULNBL_SPECTRE_V2;
 		break;
 	default:
 		panic("Unknown Loongson Processor ID!");
-- 
2.30.0


  parent reply	other threads:[~2020-12-30  3:25 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-30  3:23 [PATCH 1/3] MIPS: Add vulnerabilities infrastructure Jiaxun Yang
2020-12-30  3:23 ` [PATCH 2/3] MIPS: cpu-probe: Vulnerabilities for MIPS cores Jiaxun Yang
2020-12-31  0:31   ` Huacai Chen
2020-12-30  3:23 ` Jiaxun Yang [this message]
2020-12-31  0:33   ` [PATCH 3/3] MIPS: cpu-probe: Vulnerabilities for Loongson cores Huacai Chen
2020-12-31 15:43   ` WANG Xuerui
2020-12-31 16:09     ` Jiaxun Yang
2020-12-31  0:30 ` [PATCH 1/3] MIPS: Add vulnerabilities infrastructure Huacai Chen
2020-12-31 15:38 ` WANG Xuerui
2020-12-31 16:12   ` Jiaxun Yang

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