From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 095A1C433E0 for ; Wed, 6 Jan 2021 19:37:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC3172312E for ; Wed, 6 Jan 2021 19:37:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727294AbhAFThC (ORCPT ); Wed, 6 Jan 2021 14:37:02 -0500 Received: from mail.micronovasrl.com ([212.103.203.10]:59238 "EHLO mail.micronovasrl.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727107AbhAFThB (ORCPT ); Wed, 6 Jan 2021 14:37:01 -0500 Received: from mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) by mail.micronovasrl.com (Postfix) with ESMTP id D1720B045F1 for ; Wed, 6 Jan 2021 20:28:05 +0100 (CET) Authentication-Results: mail.micronovasrl.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=micronovasrl.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=micronovasrl.com; h=content-transfer-encoding:content-type:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :date:subject:subject:to:from:from; s=dkim; t=1609961285; x= 1610825286; bh=ve6PpitMBRMOaeoWwDbFW/+W2p3l0jAVa8GJuKa7cPU=; b=b ApMn1yPa/M9MRkOLZrYDeqI1D0qJ0zs/K4MEj3eASbCXv0hzGbkCmnpvv8YwCnR8 JzC1hi8ZRaDlTORuM0lkNBNqCmhWUSZS9kyG7GZfXdl1uUWzvuovJGZ3srZqxp9i a2JYntIWh2BNlRNSOruxcDm1PQ3Rrk8EohRME9GkRs= X-Virus-Scanned: Debian amavisd-new at mail.micronovasrl.com Received: from mail.micronovasrl.com ([127.0.0.1]) by mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id qiewOOqfVPTa for ; Wed, 6 Jan 2021 20:28:05 +0100 (CET) Received: from ubuntu.localdomain (146-241-198-163.dyn.eolo.it [146.241.198.163]) by mail.micronovasrl.com (Postfix) with ESMTPSA id D3D2DB04586; Wed, 6 Jan 2021 20:28:02 +0100 (CET) From: Giulio Benetti To: Maxime Ripard Cc: Marjan Pascolo , wens@csie.org, daniel@ffwll.ch, airlied@linux.ie, treding@nvidia.com, Jernej Skrabec , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Giulio Benetti Subject: [PATCH 2/2] drm/sun4i: tcon: improve DCLK polarity handling Date: Wed, 6 Jan 2021 20:28:00 +0100 Message-Id: <20210106192800.164052-3-giulio.benetti@micronovasrl.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210106192800.164052-1-giulio.benetti@micronovasrl.com> References: <20210106192800.164052-1-giulio.benetti@micronovasrl.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to invert DCLK polarity and this makes thing really easier than before. So let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to bus_flags the same way is done for all the other signals. Cc: Maxime Ripard Signed-off-by: Giulio Benetti --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +------------------- drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 52598bb0fb0b..30171ccd87e5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; - /* - * On A20 and similar SoCs, the only way to achieve Positive Edge - * (Rising Edge), is setting dclk clock phase to 2/3(240°). - * By default TCON works in Negative Edge(Falling Edge), - * this is why phase is set to 0 in that case. - * Unfortunately there's no way to logically invert dclk through - * IO_POL register. - * The only acceptable way to work, triple checked with scope, - * is using clock phase set to 0° for Negative Edge and set to 240° - * for Positive Edge. - * On A33 and similar SoCs there would be a 90° phase option, - * but it divides also dclk by 2. - * Following code is a way to avoid quirks all around TCON - * and DOTCLOCK drivers. - */ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) - clk_set_phase(tcon->dclk, 0); - - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - clk_set_phase(tcon->dclk, 240); + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE; regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index cfbf4e6c1679..0ce71d10a31b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -113,6 +113,7 @@ #define SUN4I_TCON0_IO_POL_REG 0x88 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27) +#define SUN4I_TCON0_IO_POL_DCLK_POSITIVE BIT(26) #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) -- 2.25.1