Hi,

On Thu, Dec 31, 2020 at 03:29:46PM +0100, Paul Kocialkowski wrote:
> The A83T supports MIPI CSI-2 with a composite controller, covering
> both the protocol logic and the D-PHY implementation. This controller
> seems to be found on the A83T only and probably was abandoned since.
> 
> This implementation splits the protocol and D-PHY registers and
> uses the PHY framework internally. The D-PHY is not registered as a
> standalone PHY driver since it cannot be used with any other
> controller.
> 
> There are a few notable points about the controller:
> - The initialisation sequence involes writing specific magic init
>   values that do not seem to make any particular sense given the
>   concerned register fields;
> - Interrupts appear to be hitting regardless of the interrupt mask
>   registers, which can cause a serious flood when transmission errors
>   occur.
> 
> Only 8-bit and 10-bit Bayer formats are currently supported.
> While up to 4 internal channels to the CSI controller exist, only one
> is currently supported by this implementation.
> 
> This work is based on the first version of the driver submitted by
> Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP.
> This version integrates MIPI CSI-2 support as a standalone V4L2 subdev
> instead of merging it in the sun6i-csi driver.
> 
> It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane
> configuration.
> 
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

There's a couple of checkpatch --strict warnings here as well

Once fixed,
Acked-by: Maxime Ripard <mripard@kernel.org>

Thanks!
Maxime