From: Zhen Lei <thunder.leizhen@huawei.com>
To: Russell King <rmk+kernel@arm.linux.org.uk>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Will Deacon <will.deacon@arm.com>,
"Haojian Zhuang" <haojian.zhuang@gmail.com>,
Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>,
Wei Xu <xuwei5@hisilicon.com>,
devicetree <devicetree@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Cc: Zhen Lei <thunder.leizhen@huawei.com>
Subject: [PATCH v3 0/3] Add Hisilicon L3 cache controller support
Date: Tue, 12 Jan 2021 09:55:59 +0800 [thread overview]
Message-ID: <20210112015602.497-1-thunder.leizhen@huawei.com> (raw)
v2 --> v3:
Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3.
v1 --> v2:
Discard the middle-tier functions and do silent narrowing cast in the outcache
hook functions. For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end)
{
+ unsigned long start = pa_start;
+ unsigned long end = pa_end;
v1:
Do cast phys_addr_t to unsigned long by adding a middle-tier function.
For example:
-static void l2c220_inv_range(unsigned long start, unsigned long end)
+static void __l2c220_inv_range(unsigned long start, unsigned long end)
{
...
}
+static void l2c220_inv_range(phys_addr_t start, phys_addr_t end)
+{
+ __l2c220_inv_range(start, end);
+}
Zhen Lei (3):
ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache
hooks
dt-bindings: arm: hisilicon: Add binding for L3 cache controller
ARM: Add Hisilicon L3 cache controller support
.../bindings/arm/hisilicon/l3cache.yaml | 37 +++++
arch/arm/include/asm/outercache.h | 6 +-
arch/arm/mm/Kconfig | 9 ++
arch/arm/mm/Makefile | 1 +
arch/arm/mm/cache-feroceon-l2.c | 15 +-
arch/arm/mm/cache-hisi-l3.c | 153 ++++++++++++++++++
arch/arm/mm/cache-hisi-l3.h | 30 ++++
arch/arm/mm/cache-l2x0.c | 50 ++++--
arch/arm/mm/cache-tauros2.c | 15 +-
arch/arm/mm/cache-uniphier.c | 6 +-
arch/arm/mm/cache-xsc3l2.c | 12 +-
11 files changed, 305 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml
create mode 100644 arch/arm/mm/cache-hisi-l3.c
create mode 100644 arch/arm/mm/cache-hisi-l3.h
--
2.26.0.106.g9fadedd
next reply other threads:[~2021-01-12 2:01 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 1:55 Zhen Lei [this message]
2021-01-12 1:56 ` [PATCH v3 1/3] ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks Zhen Lei
2021-01-12 1:56 ` [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller Zhen Lei
2021-01-12 8:46 ` Arnd Bergmann
2021-01-12 12:35 ` Leizhen (ThunderTown)
2021-01-12 13:55 ` Arnd Bergmann
2021-01-13 7:44 ` Leizhen (ThunderTown)
2021-01-13 8:13 ` Leizhen (ThunderTown)
2021-01-13 11:15 ` Arnd Bergmann
2021-01-13 12:33 ` Leizhen (ThunderTown)
2021-01-12 1:56 ` [PATCH v3 3/3] ARM: Add Hisilicon L3 cache controller support Zhen Lei
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