From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF06C433E6 for ; Tue, 12 Jan 2021 02:01:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EB59E2376F for ; Tue, 12 Jan 2021 02:01:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730581AbhALCBd (ORCPT ); Mon, 11 Jan 2021 21:01:33 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10707 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725957AbhALCBc (ORCPT ); Mon, 11 Jan 2021 21:01:32 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DFDKL1jlbzl3xG; Tue, 12 Jan 2021 09:59:34 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Tue, 12 Jan 2021 10:00:44 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller Date: Tue, 12 Jan 2021 09:56:01 +0800 Message-ID: <20210112015602.497-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20210112015602.497-1-thunder.leizhen@huawei.com> References: <20210112015602.497-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree binding for Hisilicon L3 cache controller. Signed-off-by: Zhen Lei --- .../bindings/arm/hisilicon/l3cache.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml b/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml new file mode 100644 index 000000000000000..f411818bad23741 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon L3 cache controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical + addresses. The data cached in the L3 outer cache can be operated based on the + physical address range or the entire cache. + +properties: + compatible: + items: + - const: hisilicon,l3cache + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + l3cache@f302b000 { + compatible = "hisilicon,l3cache"; + reg = <0xf302b000 0x1000>; + }; +... -- 2.26.0.106.g9fadedd