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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@somainline.org>
To: linux-arm-msm@vger.kernel.org
Cc: konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
	martin.botka@somainline.org, phone-devel@vger.kernel.org,
	robdclark@gmail.com, sean@poorly.run,
	dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
	linux-kernel@vger.kernel.org,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@somainline.org>
Subject: [PATCH v2 6/7] drm/msm/dpu: Correctly configure vsync tearcheck for command mode
Date: Tue, 12 Jan 2021 20:26:31 +0100	[thread overview]
Message-ID: <20210112192632.502897-7-angelogioacchino.delregno@somainline.org> (raw)
In-Reply-To: <20210112192632.502897-1-angelogioacchino.delregno@somainline.org>

When configuring the tearcheck, the parameters for the engine were
being set mostly as they should've been, but then it wasn't getting
configured to get the vsync indication from the TE GPIO input
because it was assumed that autorefresh could be enabled:
since a previous commit makes sure to disable the autorefresh bit
when committing to the cmd engine, it is now safe to just enable
the vsync pin input at tearcheck setup time (instead of erroneously
never enabling it).

Also, set the right sync_cfg_height to enable the DPU auto-generated
TE signal in order to avoid stalls in the event that we miss one
external TE signal: this will still trigger recovery mechanisms in
case the display is really unreachable.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 4d3481baaead..665eb1d4cb8a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -372,15 +372,12 @@ static void dpu_encoder_phys_cmd_tearcheck_config(
 	tc_cfg.vsync_count = vsync_hz /
 				(mode->vtotal * drm_mode_vrefresh(mode));
 
-	/* enable external TE after kickoff to avoid premature autorefresh */
-	tc_cfg.hw_vsync_mode = 0;
-
 	/*
-	 * By setting sync_cfg_height to near max register value, we essentially
-	 * disable dpu hw generated TE signal, since hw TE will arrive first.
-	 * Only caveat is if due to error, we hit wrap-around.
+	 * Set the sync_cfg_height to twice vtotal so that if we lose a
+	 * TE event coming from the display TE pin we won't stall immediately
 	 */
-	tc_cfg.sync_cfg_height = 0xFFF0;
+	tc_cfg.hw_vsync_mode = 1;
+	tc_cfg.sync_cfg_height = mode->vtotal * 2;
 	tc_cfg.vsync_init_val = mode->vdisplay;
 	tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START;
 	tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE;
-- 
2.29.2


  parent reply	other threads:[~2021-01-12 19:28 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-12 19:26 [PATCH v2 0/7] Qualcomm DRM DPU fixes AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 1/7] drm/msm/dpu: Fix VBIF_XINL_QOS_LVL_REMAP_000 register offset AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 2/7] drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 3/7] drm/msm/dpu: Add prog_fetch_lines_worst_case to INTF_BLK macro AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 4/7] drm/msm/dpu: Allow specifying features and sblk in DSPP_BLK macro AngeloGioacchino Del Regno
2021-01-12 19:26 ` [PATCH v2 5/7] drm/msm/dpu: Disable autorefresh in command mode AngeloGioacchino Del Regno
2021-01-12 19:26 ` AngeloGioacchino Del Regno [this message]
2021-01-12 19:26 ` [PATCH v2 7/7] drm/msm/dpu: Remove unused call in wait_for_commit_done AngeloGioacchino Del Regno
2021-05-15 23:04 ` [PATCH v2 0/7] Qualcomm DRM DPU fixes Dmitry Baryshkov

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