From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47B03C4332E for ; Tue, 19 Jan 2021 09:41:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10F2F23135 for ; Tue, 19 Jan 2021 09:41:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732736AbhASJYC (ORCPT ); Tue, 19 Jan 2021 04:24:02 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:12791 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729343AbhASI4s (ORCPT ); Tue, 19 Jan 2021 03:56:48 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Tue, 19 Jan 2021 00:56:00 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Jan 2021 08:55:58 +0000 Received: from jckuo-lt.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Tue, 19 Jan 2021 08:55:55 +0000 From: JC Kuo To: , , , , CC: , , , , , JC Kuo , Thierry Reding Subject: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init Date: Tue, 19 Jan 2021 16:55:33 +0800 Message-ID: <20210119085546.725005-3-jckuo@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210119085546.725005-1-jckuo@nvidia.com> References: <20210119085546.725005-1-jckuo@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611046560; bh=gguPJ5VOzO9Vc3llEbIEJZuHhChUK6oYDayYAJFTFkY=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=AEQf96b6t3e48HhCcymBZfArgK8iHjQ7FejHKvkNmh8CaDA5O3u+YLwGyGy6Ze3Q5 NI6sJ9OxOo5E4zUEZioJDAuonbSCXQElXvf6N1C9gao97oGu3uS0gMhzpqv0MG45dj B78U4loL7q1RXUYIwcl+VfZdmyB/9jBf1z3ZC7B1lWy7Fr9A+lYE1Bs1bSmMSnup+s GhflA2OefSfKFU/+rQlU+f+4vovVfYVprlpv8KsUb8rDlFi60Leu9SEY4Pn0cCH4V5 Ns32p2jM3PSudl8YsY6iuZ+PdW/MBngwFvNBs7Qe0lZSGiSbyMNrc7NUfJaPIIiwxQ pKOsEUuG7BcRQ== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- v6: no change v5: no change v4: no change=20 v3: no change drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *h= w) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); =20 - val =3D pll_readl_misc(pll); - val &=3D ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val =3D pll_readl(pll->params->aux_reg, pll); - val |=3D (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &=3D ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |=3D PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags); --=20 2.25.1