From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04B36C433E0 for ; Wed, 20 Jan 2021 19:54:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A92A823441 for ; Wed, 20 Jan 2021 19:54:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392664AbhATTyg (ORCPT ); Wed, 20 Jan 2021 14:54:36 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42296 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388145AbhATTxE (ORCPT ); Wed, 20 Jan 2021 14:53:04 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 10KJpmYF027733; Wed, 20 Jan 2021 13:51:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1611172309; bh=zraMxWl53AJvGoFoRAMNuY64tWhjj2qsiF8PytLxV5Q=; h=From:To:CC:Subject:Date; b=lcAUF+UQf0Wp0qLHdeMWkxTOOMs5itACevOxf9aPPnLEsjpLavdzR1Ru7PKADy1ax iNqVZ8My9/TD3nxvczTRbQCckJhbHYaDKYBXxXy9oiczZccprAZ8rqRxg+GGR6fGtm luSvuTRNVJS1+QksfnadqD8Z5CJupGymKQ+4oPZU= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 10KJpmws030331 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 20 Jan 2021 13:51:48 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 20 Jan 2021 13:51:48 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 20 Jan 2021 13:51:48 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 10KJpm3S015445; Wed, 20 Jan 2021 13:51:48 -0600 From: Nishanth Menon To: Sudeep Holla , Suman Anna , Dave Gerlach CC: Tero Kristo , Rob Herring , , , , Nishanth Menon Subject: [PATCH] arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific Date: Wed, 20 Jan 2021 13:51:45 -0600 Message-ID: <20210120195145.32259-1-nm@ti.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b814c1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We can use CPU specific pmu configuration to expose the appropriate CPU specific events rather than just the basic generic pmuv3 perf events. Reported-by: Sudeep Holla Signed-off-by: Nishanth Menon --- AM65: https://pastebin.ubuntu.com/p/TF2cCMySkt/ J721E: https://pastebin.ubuntu.com/p/jgGPNmNgG3/ J7200: https://pastebin.ubuntu.com/p/Kfc3VHHXNB/ Original report: https://lore.kernel.org/linux-arm-kernel/20210119172412.smsjdo2sjzqi5vcn@bogus/ I have'nt split this patch up for fixes tag primarily because the basic functionality works and this is an improvement than a critical fixup to backport for older kernels. arch/arm64/boot/dts/ti/k3-am65.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index d84c0bc05023..a9fc1af03f27 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -56,7 +56,7 @@ a53_timer0: timer-cl0-cpu0 { }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = ; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 66169bcf7c9a..b7005b803149 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -114,7 +114,7 @@ a72_timer0: timer-cl0-cpu0 { }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index cc483f7344af..f0587fde147e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -115,7 +115,7 @@ a72_timer0: timer-cl0-cpu0 { }; pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; /* Recommendation from GIC500 TRM Table A.3 */ interrupts = ; }; -- 2.25.1.377.g2d2118b814c1