From: Sia Jee Heng <jee.heng.sia@intel.com>
To: vkoul@kernel.org, Eugeniy.Paltsev@synopsys.com, robh+dt@kernel.org
Cc: andriy.shevchenko@linux.intel.com, jee.heng.sia@intel.com,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v10 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
Date: Thu, 21 Jan 2021 13:56:39 +0800 [thread overview]
Message-ID: <20210121055641.6307-15-jee.heng.sia@intel.com> (raw)
In-Reply-To: <20210121055641.6307-1-jee.heng.sia@intel.com>
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index e19369f9365a..ea527b92e0fc 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,30 @@ static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
axi_chan_iowrite64(chan, CH_LLP, adr);
}
+static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
+{
+ u32 reg_width, offset, val;
+
+ if (!chan->chip->apb_regs) {
+ dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
+ return;
+ }
+
+ reg_width = __ffs(chan->config.dst_addr_width);
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_8)
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ else if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+
+ val = ioread32(chan->chip->apb_regs + offset);
+
+ if (set)
+ val |= BIT(chan->id);
+ else
+ val &= ~BIT(chan->id);
+
+ iowrite32(val, chan->chip->apb_regs + offset);
+}
/* Called in chan locked context */
static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
struct axi_dma_desc *first)
@@ -334,6 +358,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ dw_axi_dma_set_byte_halfword(chan, true);
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -1008,6 +1033,8 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
if (chan->direction != DMA_MEM_TO_MEM)
dw_axi_dma_set_hw_channel(chan->chip,
chan->hw_handshake_num, false);
+ if (chan->direction == DMA_MEM_TO_DEV)
+ dw_axi_dma_set_byte_halfword(chan, false);
spin_lock_irqsave(&chan->vc.lock, flags);
--
2.18.0
next prev parent reply other threads:[~2021-01-21 6:23 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-21 5:56 [PATCH v10 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 02/16] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 05/16] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
2021-01-22 7:22 ` kernel test robot
2021-01-21 5:56 ` [PATCH v10 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
2021-01-21 5:56 ` Sia Jee Heng [this message]
2021-01-21 9:20 ` [PATCH v10 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers kernel test robot
2021-01-21 5:56 ` [PATCH v10 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
2021-01-21 5:56 ` [PATCH v10 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
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