* [PATCH 0/4] Add Support for SM8350 UFS
@ 2021-01-25 10:09 Vinod Koul
2021-01-25 10:09 ` [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings Vinod Koul
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Vinod Koul @ 2021-01-25 10:09 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Martin K . Petersen
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Rob Herring, Manu Gautam, James E . J . Bottomley, Asutosh Das,
devicetree, linux-kernel
This series adds support for UFS found in SM8350 SoC. First we add UFS HC
compatible strings, along with missing one for SM8250. This can go thru SCSI
subssystem.
Then we add binding for UFS phy and new regsiters and nw offsets specific to
SM8350 followed by UFS phy tables. This can go thru phy subsystem.
Vinod Koul (4):
scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings
dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
phy: qcom-qmp: Add UFS v4 registers found in SM8350
phy: qcom-qmp: Add support for SM8350 UFS phy
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 2 +
drivers/phy/qualcomm/phy-qcom-qmp.c | 127 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.h | 27 ++++
4 files changed, 157 insertions(+)
--
2.26.2
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings
2021-01-25 10:09 [PATCH 0/4] Add Support for SM8350 UFS Vinod Koul
@ 2021-01-25 10:09 ` Vinod Koul
2021-01-25 17:10 ` Bjorn Andersson
2021-01-25 10:09 ` [PATCH 2/4] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Vinod Koul @ 2021-01-25 10:09 UTC (permalink / raw)
To: Martin K . Petersen
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul,
James E . J . Bottomley, Asutosh Das, Rob Herring, devicetree,
linux-kernel
Document "qcom,sm8250-ufshc" and "qcom,sm8350-ufshc" compatible string.
Use of "qcom,sm8250-ufshc" is already present upstream, so add misiing
documentation. "qcom,sm8350-ufshc" is for UFS HC found in SM8350 SoC.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
index 415ccdd7442d..d8fd4df81743 100644
--- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
@@ -14,6 +14,8 @@ Required properties:
"qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
"qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
"qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
+ "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
+ "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
- interrupts : <interrupt mapping for UFS host controller IRQ>
- reg : <registers mapping>
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/4] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
2021-01-25 10:09 [PATCH 0/4] Add Support for SM8350 UFS Vinod Koul
2021-01-25 10:09 ` [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings Vinod Koul
@ 2021-01-25 10:09 ` Vinod Koul
2021-01-25 17:10 ` Bjorn Andersson
2021-01-25 10:09 ` [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350 Vinod Koul
2021-01-25 10:09 ` [PATCH 4/4] phy: qcom-qmp: Add support for SM8350 UFS phy Vinod Koul
3 siblings, 1 reply; 10+ messages in thread
From: Vinod Koul @ 2021-01-25 10:09 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Rob Herring, Manu Gautam, Asutosh Das, linux-kernel, devicetree
Add the compatible strings for the UFS PHY found on SM8350 SoC.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 62c4f2ba5b9f..bf804c12fa5f 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -38,6 +38,7 @@ properties:
- qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8250-qmp-usb3-phy
- qcom,sm8250-qmp-usb3-uni-phy
+ - qcom,sm8350-qmp-ufs-phy
- qcom,sm8350-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-uni-phy
- qcom,sdx55-qmp-usb3-uni-phy
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350
2021-01-25 10:09 [PATCH 0/4] Add Support for SM8350 UFS Vinod Koul
2021-01-25 10:09 ` [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings Vinod Koul
2021-01-25 10:09 ` [PATCH 2/4] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
@ 2021-01-25 10:09 ` Vinod Koul
2021-01-25 17:11 ` Bjorn Andersson
2021-01-25 17:36 ` Jack Pham
2021-01-25 10:09 ` [PATCH 4/4] phy: qcom-qmp: Add support for SM8350 UFS phy Vinod Koul
3 siblings, 2 replies; 10+ messages in thread
From: Vinod Koul @ 2021-01-25 10:09 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Asutosh Das, linux-kernel
Add the registers for few new registers found in SM8350. Also the UFS
phy used in SM8350 seems to have different offsets than V4 phy, although
it claims it is v4 phy, so add the new offsets with SM8350 tag instead
of V4 tag.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index dff7be5a1cc1..bba1d5e3eb73 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -451,6 +451,7 @@
#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
#define QSERDES_V4_TX_LANE_MODE_1 0x84
#define QSERDES_V4_TX_LANE_MODE_2 0x88
+#define QSERDES_V4_TX_LANE_MODE_3 0x8C
#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
@@ -459,6 +460,13 @@
#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
#define QSERDES_V4_TX_PI_QEC_CTRL 0x104
+/* Only for SM8350 QMP V4 Phy TX offsets different from V4 */
+#define QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
+#define QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
+#define QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
+#define QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
+#define QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN 0xc0
+
/* Only for QMP V4 PHY - RX registers */
#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
@@ -514,6 +522,24 @@
#define QSERDES_V4_RX_DCC_CTRL1 0x1bc
#define QSERDES_V4_RX_VTH_CODE 0x1c4
+/* Only for SM8350 QMP V4 Phy RX offsets different from V4 */
+#define QSERDES_SM8350_RX_RX_MODE_00_LOW 0x15c
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH 0x160
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH2 0x164
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH3 0x168
+#define QSERDES_SM8350_RX_RX_MODE_00_HIGH4 0x16c
+#define QSERDES_SM8350_RX_RX_MODE_01_LOW 0x170
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH 0x174
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH2 0x178
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH3 0x17c
+#define QSERDES_SM8350_RX_RX_MODE_01_HIGH4 0x180
+#define QSERDES_SM8350_RX_RX_MODE_10_LOW 0x184
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH 0x188
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH2 0x18c
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH3 0x190
+#define QSERDES_SM8350_RX_RX_MODE_10_HIGH4 0x194
+#define QSERDES_SM8350_RX_DCC_CTRL1 0x1a8
+
/* Only for QMP V4 PHY - UFS PCS registers */
#define QPHY_V4_PCS_UFS_PHY_START 0x000
#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
@@ -529,6 +555,7 @@
#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
+#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1 0x154
#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/4] phy: qcom-qmp: Add support for SM8350 UFS phy
2021-01-25 10:09 [PATCH 0/4] Add Support for SM8350 UFS Vinod Koul
` (2 preceding siblings ...)
2021-01-25 10:09 ` [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350 Vinod Koul
@ 2021-01-25 10:09 ` Vinod Koul
2021-01-25 17:11 ` Bjorn Andersson
3 siblings, 1 reply; 10+ messages in thread
From: Vinod Koul @ 2021-01-25 10:09 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Asutosh Das, linux-kernel
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 127 ++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index dbc12a19b702..4a9d1010910d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1983,6 +1983,106 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
};
+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x65),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+
+ /* Rate B */
+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
+};
+
+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xf5),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH4, 0x3c),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH4, 0xb7),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_LOW, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH3, 0x3b),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH4, 0xb7),
+ QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_DCC_CTRL1, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+};
+
static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
@@ -2971,6 +3071,30 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
};
+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
+ .type = PHY_TYPE_UFS,
+ .nlanes = 2,
+
+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
+ .tx_tbl = sm8350_ufsphy_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
+ .rx_tbl = sm8350_ufsphy_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
+ .clk_list = sdm845_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8150_ufsphy_regs_layout,
+
+ .start_ctrl = SERDES_START,
+ .pwrdn_ctrl = SW_PWRDN,
+
+ .is_dual_lane_phy = true,
+};
+
static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -4379,6 +4503,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, {
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sm8350-qmp-ufs-phy",
+ .data = &sm8350_ufsphy_cfg,
}, {
.compatible = "qcom,sm8350-qmp-usb3-phy",
.data = &sm8350_usb3phy_cfg,
--
2.26.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings
2021-01-25 10:09 ` [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings Vinod Koul
@ 2021-01-25 17:10 ` Bjorn Andersson
0 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2021-01-25 17:10 UTC (permalink / raw)
To: Vinod Koul
Cc: Martin K . Petersen, linux-arm-msm, James E . J . Bottomley,
Asutosh Das, Rob Herring, devicetree, linux-kernel
On Mon 25 Jan 04:09 CST 2021, Vinod Koul wrote:
> Document "qcom,sm8250-ufshc" and "qcom,sm8350-ufshc" compatible string.
> Use of "qcom,sm8250-ufshc" is already present upstream, so add misiing
> documentation. "qcom,sm8350-ufshc" is for UFS HC found in SM8350 SoC.
>
This can/should be picked up independently of the other patches, so
would have been better sent solo.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
> index 415ccdd7442d..d8fd4df81743 100644
> --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
> +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
> @@ -14,6 +14,8 @@ Required properties:
> "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
> "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
> "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
> + "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
> + "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"
> - interrupts : <interrupt mapping for UFS host controller IRQ>
> - reg : <registers mapping>
>
> --
> 2.26.2
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/4] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
2021-01-25 10:09 ` [PATCH 2/4] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
@ 2021-01-25 17:10 ` Bjorn Andersson
0 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2021-01-25 17:10 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, linux-arm-msm, Andy Gross, Rob Herring,
Manu Gautam, Asutosh Das, linux-kernel, devicetree
On Mon 25 Jan 04:09 CST 2021, Vinod Koul wrote:
> Add the compatible strings for the UFS PHY found on SM8350 SoC.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> index 62c4f2ba5b9f..bf804c12fa5f 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> @@ -38,6 +38,7 @@ properties:
> - qcom,sm8250-qmp-modem-pcie-phy
> - qcom,sm8250-qmp-usb3-phy
> - qcom,sm8250-qmp-usb3-uni-phy
> + - qcom,sm8350-qmp-ufs-phy
> - qcom,sm8350-qmp-usb3-phy
> - qcom,sm8350-qmp-usb3-uni-phy
> - qcom,sdx55-qmp-usb3-uni-phy
> --
> 2.26.2
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350
2021-01-25 10:09 ` [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350 Vinod Koul
@ 2021-01-25 17:11 ` Bjorn Andersson
2021-01-25 17:36 ` Jack Pham
1 sibling, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2021-01-25 17:11 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, linux-arm-msm, Andy Gross, Asutosh Das,
linux-kernel
On Mon 25 Jan 04:09 CST 2021, Vinod Koul wrote:
> Add the registers for few new registers found in SM8350. Also the UFS
> phy used in SM8350 seems to have different offsets than V4 phy, although
> it claims it is v4 phy, so add the new offsets with SM8350 tag instead
> of V4 tag.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index dff7be5a1cc1..bba1d5e3eb73 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -451,6 +451,7 @@
> #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
> #define QSERDES_V4_TX_LANE_MODE_1 0x84
> #define QSERDES_V4_TX_LANE_MODE_2 0x88
> +#define QSERDES_V4_TX_LANE_MODE_3 0x8C
> #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
> #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
> #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
> @@ -459,6 +460,13 @@
> #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
> #define QSERDES_V4_TX_PI_QEC_CTRL 0x104
>
> +/* Only for SM8350 QMP V4 Phy TX offsets different from V4 */
> +#define QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
> +#define QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
> +#define QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
> +#define QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
> +#define QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN 0xc0
> +
> /* Only for QMP V4 PHY - RX registers */
> #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
> #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
> @@ -514,6 +522,24 @@
> #define QSERDES_V4_RX_DCC_CTRL1 0x1bc
> #define QSERDES_V4_RX_VTH_CODE 0x1c4
>
> +/* Only for SM8350 QMP V4 Phy RX offsets different from V4 */
> +#define QSERDES_SM8350_RX_RX_MODE_00_LOW 0x15c
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH 0x160
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH2 0x164
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH3 0x168
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH4 0x16c
> +#define QSERDES_SM8350_RX_RX_MODE_01_LOW 0x170
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH 0x174
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH2 0x178
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH3 0x17c
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH4 0x180
> +#define QSERDES_SM8350_RX_RX_MODE_10_LOW 0x184
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH 0x188
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH2 0x18c
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH3 0x190
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH4 0x194
> +#define QSERDES_SM8350_RX_DCC_CTRL1 0x1a8
> +
> /* Only for QMP V4 PHY - UFS PCS registers */
> #define QPHY_V4_PCS_UFS_PHY_START 0x000
> #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
> @@ -529,6 +555,7 @@
> #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
> #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
> #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
> +#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1 0x154
> #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
> #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
> #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
> --
> 2.26.2
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] phy: qcom-qmp: Add support for SM8350 UFS phy
2021-01-25 10:09 ` [PATCH 4/4] phy: qcom-qmp: Add support for SM8350 UFS phy Vinod Koul
@ 2021-01-25 17:11 ` Bjorn Andersson
0 siblings, 0 replies; 10+ messages in thread
From: Bjorn Andersson @ 2021-01-25 17:11 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, linux-arm-msm, Andy Gross, Asutosh Das,
linux-kernel
On Mon 25 Jan 04:09 CST 2021, Vinod Koul wrote:
> Add the tables for init sequences for UFS QMP phy found in SM8350 SoC.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 127 ++++++++++++++++++++++++++++
> 1 file changed, 127 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
> index dbc12a19b702..4a9d1010910d 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
> @@ -1983,6 +1983,106 @@ static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
> QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
> };
>
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x19),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x65),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
> +
> + /* Rate B */
> + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xf5),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x3f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
> + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_LOW, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH, 0x6d),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH2, 0xed),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_00_HIGH4, 0x3c),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_01_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_LOW, 0xe0),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH2, 0xc8),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH3, 0x3b),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_RX_MODE_10_HIGH4, 0xb7),
> + QMP_PHY_INIT_CFG(QSERDES_SM8350_RX_DCC_CTRL1, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
> @@ -2971,6 +3071,30 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
> .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
> };
>
> +static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> + .type = PHY_TYPE_UFS,
> + .nlanes = 2,
> +
> + .serdes_tbl = sm8350_ufsphy_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
> + .tx_tbl = sm8350_ufsphy_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
> + .rx_tbl = sm8350_ufsphy_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
> + .pcs_tbl = sm8350_ufsphy_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sm8150_ufsphy_regs_layout,
> +
> + .start_ctrl = SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN,
> +
> + .is_dual_lane_phy = true,
> +};
> +
> static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
> .type = PHY_TYPE_USB3,
> .nlanes = 1,
> @@ -4379,6 +4503,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
> }, {
> .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
> .data = &sm8250_qmp_gen3x2_pciephy_cfg,
> + }, {
> + .compatible = "qcom,sm8350-qmp-ufs-phy",
> + .data = &sm8350_ufsphy_cfg,
> }, {
> .compatible = "qcom,sm8350-qmp-usb3-phy",
> .data = &sm8350_usb3phy_cfg,
> --
> 2.26.2
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350
2021-01-25 10:09 ` [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350 Vinod Koul
2021-01-25 17:11 ` Bjorn Andersson
@ 2021-01-25 17:36 ` Jack Pham
1 sibling, 0 replies; 10+ messages in thread
From: Jack Pham @ 2021-01-25 17:36 UTC (permalink / raw)
To: Vinod Koul
Cc: Kishon Vijay Abraham I, linux-arm-msm, Bjorn Andersson,
Andy Gross, Asutosh Das, linux-kernel
Hi Vinod,
On Mon, Jan 25, 2021 at 03:39:05PM +0530, Vinod Koul wrote:
> Add the registers for few new registers found in SM8350. Also the UFS
> phy used in SM8350 seems to have different offsets than V4 phy, although
> it claims it is v4 phy, so add the new offsets with SM8350 tag instead
> of V4 tag.
Actually I believe SM8350 UFS PHY is on V5, as the internal IP revision
shows 5.0.0. So IMO some of the below definitions should just be using
the V5 macros for consistency with the ones I recently added for USB3.
And like USB3 QMP, it seems we have mixed usage of V4/V5 macros in the
sequence tables, mainly wherever the offsets are identical between IP
revisions. Hope this doesn't turn out to be a maintenance nightmare...
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
> index dff7be5a1cc1..bba1d5e3eb73 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
> @@ -451,6 +451,7 @@
> #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
> #define QSERDES_V4_TX_LANE_MODE_1 0x84
> #define QSERDES_V4_TX_LANE_MODE_2 0x88
> +#define QSERDES_V4_TX_LANE_MODE_3 0x8C
> #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
> #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
> #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
> @@ -459,6 +460,13 @@
> #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
> #define QSERDES_V4_TX_PI_QEC_CTRL 0x104
>
> +/* Only for SM8350 QMP V4 Phy TX offsets different from V4 */
> +#define QSERDES_SM8350_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
> +#define QSERDES_SM8350_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
> +#define QSERDES_SM8350_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
> +#define QSERDES_SM8350_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
> +#define QSERDES_SM8350_TX_TRAN_DRVR_EMP_EN 0xc0
These could be augmented to the V5 TX defintions? Although they are not
present for USB, so not sure if you want to add "V5_UFS" to the prefix.
But since they are at offsets past the end of the USB TX bank it should
also be ok to share in the QSERDES_V5_TX namespace.
> +
> /* Only for QMP V4 PHY - RX registers */
> #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
> #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
> @@ -514,6 +522,24 @@
> #define QSERDES_V4_RX_DCC_CTRL1 0x1bc
> #define QSERDES_V4_RX_VTH_CODE 0x1c4
>
> +/* Only for SM8350 QMP V4 Phy RX offsets different from V4 */
> +#define QSERDES_SM8350_RX_RX_MODE_00_LOW 0x15c
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH 0x160
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH2 0x164
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH3 0x168
> +#define QSERDES_SM8350_RX_RX_MODE_00_HIGH4 0x16c
> +#define QSERDES_SM8350_RX_RX_MODE_01_LOW 0x170
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH 0x174
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH2 0x178
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH3 0x17c
> +#define QSERDES_SM8350_RX_RX_MODE_01_HIGH4 0x180
> +#define QSERDES_SM8350_RX_RX_MODE_10_LOW 0x184
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH 0x188
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH2 0x18c
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH3 0x190
> +#define QSERDES_SM8350_RX_RX_MODE_10_HIGH4 0x194
> +#define QSERDES_SM8350_RX_DCC_CTRL1 0x1a8
These are identical to the "V5" offsets I had added for SM8350 USB.
Thanks,
Jack
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-01-26 20:07 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-25 10:09 [PATCH 0/4] Add Support for SM8350 UFS Vinod Koul
2021-01-25 10:09 ` [PATCH 1/4] scsi: dt-bindings: ufs: Add sm8250, sm8350 compatible strings Vinod Koul
2021-01-25 17:10 ` Bjorn Andersson
2021-01-25 10:09 ` [PATCH 2/4] dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings Vinod Koul
2021-01-25 17:10 ` Bjorn Andersson
2021-01-25 10:09 ` [PATCH 3/4] phy: qcom-qmp: Add UFS v4 registers found in SM8350 Vinod Koul
2021-01-25 17:11 ` Bjorn Andersson
2021-01-25 17:36 ` Jack Pham
2021-01-25 10:09 ` [PATCH 4/4] phy: qcom-qmp: Add support for SM8350 UFS phy Vinod Koul
2021-01-25 17:11 ` Bjorn Andersson
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