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From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>
Cc: "Jernej Skrabec" <jernej.skrabec@siol.net>,
	"Samuel Holland" <samuel@sholland.org>,
	"Icenowy Zheng" <icenowy@aosc.io>,
	"Rob Herring" <robh@kernel.org>,
	"Clément Péron" <peron.clem@gmail.com>,
	"Shuosheng Huang" <huangshuosheng@allwinnertech.com>,
	"Yangtao Li" <tiny.windzz@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
	devicetree@vger.kernel.org
Subject: [PATCH v5 20/20] arm64: dts: allwinner: Add OrangePi Zero 2 .dts
Date: Wed, 27 Jan 2021 17:25:00 +0000	[thread overview]
Message-ID: <20210127172500.13356-21-andre.przywara@arm.com> (raw)
In-Reply-To: <20210127172500.13356-1-andre.przywara@arm.com>

The OrangePi Zero 2 is a development board with the new H616 SoC.

It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.

For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/allwinner/Makefile        |   1 +
 .../allwinner/sun50i-h616-orangepi-zero2.dts  | 203 ++++++++++++++++++
 2 files changed, 204 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts

diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 41ce680e5f8d..9ba4b5d92657 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index 000000000000..ca07cae698ce
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "OrangePi Zero2";
+	compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+	aliases {
+		ethernet0 = &emac0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			function = LED_FUNCTION_POWER;
+			color = <LED_COLOR_ID_RED>;
+			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+			default-state = "on";
+		};
+
+		led-1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+		};
+	};
+
+	reg_vcc5v: vcc5v {
+		/* board wide 5V supply directly from the USB-C socket */
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+};
+
+&emac0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&ext_rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-handle = <&ext_rgmii_phy>;
+	phy-supply = <&reg_dcdce>;
+	allwinner,rx-delay-ps = <3100>;
+	allwinner,tx-delay-ps = <700>;
+	status = "okay";
+};
+
+&mdio0 {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_dcdce>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
+	bus-width = <4>;
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+
+	axp305: pmic@745 {
+		compatible = "x-powers,axp305", "x-powers,axp805",
+			     "x-powers,axp806";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		reg = <0x745>;
+
+		x-powers,self-working-mode;
+		vina-supply = <&reg_vcc5v>;
+		vinb-supply = <&reg_vcc5v>;
+		vinc-supply = <&reg_vcc5v>;
+		vind-supply = <&reg_vcc5v>;
+		vine-supply = <&reg_vcc5v>;
+		aldoin-supply = <&reg_vcc5v>;
+		bldoin-supply = <&reg_vcc5v>;
+		cldoin-supply = <&reg_vcc5v>;
+
+		regulators {
+			reg_aldo1: aldo1 {
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-sys";
+			};
+
+			reg_aldo2: aldo2 {	/* 3.3V on headers */
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3-ext";
+			};
+
+			reg_aldo3: aldo3 {	/* 3.3V on headers */
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3-ext2";
+			};
+
+			reg_bldo1: bldo1 {
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc1v8";
+			};
+
+			bldo2 {
+				/* unused */
+			};
+
+			bldo3 {
+				/* unused */
+			};
+
+			bldo4 {
+				/* unused */
+			};
+
+			cldo1 {
+				/* reserved */
+			};
+
+			cldo2 {
+				/* unused */
+			};
+
+			cldo3 {
+				/* unused */
+			};
+
+			reg_dcdca: dcdca {
+				regulator-always-on;
+				regulator-min-microvolt = <810000>;
+				regulator-max-microvolt = <1080000>;
+				regulator-name = "vdd-cpu";
+			};
+
+			reg_dcdcc: dcdcc {
+				regulator-always-on;
+				regulator-min-microvolt = <810000>;
+				regulator-max-microvolt = <1080000>;
+				regulator-name = "vdd-gpu-sys";
+			};
+
+			reg_dcdcd: dcdcd {
+				regulator-always-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vdd-dram";
+			};
+
+			reg_dcdce: dcdce {
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc-eth-mmc";
+			};
+
+			sw {
+				/* unused */
+			};
+		};
+	};
+};
+
+&spi0  {
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_ph_pins>;
+	status = "okay";
+};
-- 
2.17.5


      parent reply	other threads:[~2021-01-27 17:32 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-27 17:24 [PATCH v5 00/20] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2021-01-27 17:24 ` [PATCH v5 01/20] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 Andre Przywara
2021-01-27 17:24 ` [PATCH v5 02/20] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara
2021-01-27 17:24 ` [PATCH v5 03/20] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara
2021-01-27 17:24 ` [PATCH v5 04/20] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ) Andre Przywara
2021-01-28 10:15   ` Maxime Ripard
2021-02-02  7:55   ` [linux-sunxi] " Chen-Yu Tsai
2021-02-02 10:11     ` Andre Przywara
2021-02-05 21:56   ` Rob Herring
2021-01-27 17:24 ` [PATCH v5 05/20] Input: axp20x-pek: Bail out if AXP has no interrupt line connected Andre Przywara
2021-01-27 19:42   ` Dmitry Torokhov
2021-01-28 11:11     ` Andre Przywara
2021-01-28 11:36       ` Mark Brown
2021-01-28 12:31         ` Andre Przywara
2021-01-28 15:05           ` Mark Brown
2021-01-27 17:24 ` [PATCH v5 06/20] mfd: axp20x: Allow AXP chips without interrupt lines Andre Przywara
2021-01-28 10:15   ` Maxime Ripard
2021-02-02  7:58     ` [linux-sunxi] " Chen-Yu Tsai
2021-02-02  8:12   ` Lee Jones
2021-01-27 17:24 ` [PATCH v5 07/20] dt-bindings: sram: sunxi-sram: Add H616 compatible string Andre Przywara
2021-01-27 17:24 ` [PATCH v5 08/20] soc: sunxi: sram: Add support for more than one EMAC clock Andre Przywara
2021-01-27 17:24 ` [PATCH v5 09/20] dt-bindings: watchdog: sun4i: Add H616 compatible string Andre Przywara
2021-01-27 17:24 ` [PATCH v5 10/20] dt-bindings: i2c: mv64xxx: " Andre Przywara
2021-01-28  8:44   ` Wolfram Sang
2021-01-27 17:24 ` [PATCH v5 11/20] dt-bindings: media: IR: Add H616 IR " Andre Przywara
2021-01-27 17:24 ` [PATCH v5 12/20] dt-bindings: rtc: sun6i: Add H616 " Andre Przywara
2021-01-28 10:20   ` Maxime Ripard
     [not found]   ` <1675074.8rG671tKPg@kista>
2021-02-02  0:05     ` Andre Przywara
2021-01-27 17:24 ` [PATCH v5 13/20] dt-bindings: spi: sunxi: " Andre Przywara
2021-01-27 17:24 ` [PATCH v5 14/20] dt-bindings: bus: rsb: " Andre Przywara
2021-02-02  7:57   ` Chen-Yu Tsai
2021-01-27 17:24 ` [PATCH v5 15/20] dt-bindings: net: sun8i-emac: " Andre Przywara
2021-01-28 10:21   ` Maxime Ripard
2021-02-05 21:58   ` Rob Herring
2021-01-27 17:24 ` [PATCH v5 16/20] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara
2021-01-28 10:21   ` Maxime Ripard
2021-01-27 17:24 ` [PATCH v5 17/20] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling Andre Przywara
2021-01-27 17:24 ` [PATCH v5 18/20] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2021-01-27 17:24 ` [PATCH v5 19/20] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara
2021-01-27 17:25 ` Andre Przywara [this message]

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