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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Boris Brezillon <boris.brezillon@collabora.com>,
	richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	bjorn.andersson@linaro.org
Subject: Re: [PATCH] mtd: rawnand: Do not check for bad block if bbt is unavailable
Date: Thu, 4 Feb 2021 09:13:36 +0100	[thread overview]
Message-ID: <20210204091336.1406ca3b@xps13> (raw)
In-Reply-To: <F55F9D7B-0542-448E-A711-D1035E467ACA@linaro.org>

Hi Manivannan,

Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote on Wed,
03 Feb 2021 17:11:31 +0530:

> On 3 February 2021 4:54:22 PM IST, Boris Brezillon <boris.brezillon@collabora.com> wrote:
> >On Wed, 03 Feb 2021 16:22:42 +0530
> >Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> >  
> >> On 3 February 2021 3:49:14 PM IST, Boris Brezillon  
> ><boris.brezillon@collabora.com> wrote:  
> >> >On Wed, 03 Feb 2021 15:42:02 +0530
> >> >Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> >> >    
> >> >> >> 
> >> >> >> I got more information from the vendor, Telit. The access to  
> >the    
> >> >3rd      
> >> >> >partition is protected by Trustzone and any access in non  
> >privileged  
> >> >> >mode (where Linux kernel runs) causes kernel panic and the device
> >> >> >reboots.     
> >> >
> >> >Out of curiosity, is it a per-CS-line thing or is this section
> >> >protected on all CS?
> >> >    
> >> 
> >> Sorry, I didn't get your question.   
> >
> >The qcom controller can handle several chips, each connected through a
> >different CS (chip-select) line, right? I'm wondering if the firmware
> >running in secure mode has the ability to block access for a specific
> >CS line or if all CS lines have the same constraint. That will impact
> >the way you describe it in your DT (in one case the secure-region
> >property should be under the controller node, in the other case it
> >should be under the NAND chip node).  
> 
> Right. I believe the implementation is common to all NAND chips so the property should be in the controller node. 

Looks weird: do you mean that each of the chips will have a secure area?

  reply	other threads:[~2021-02-04  8:14 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-30  3:54 [PATCH] mtd: rawnand: Do not check for bad block if bbt is unavailable Manivannan Sadhasivam
2021-02-01 14:18 ` Miquel Raynal
2021-02-02  4:16   ` Manivannan Sadhasivam
2021-02-02  8:14     ` Miquel Raynal
2021-02-03  9:58       ` Manivannan Sadhasivam
2021-02-03 10:05         ` Miquel Raynal
2021-02-03 10:12           ` Manivannan Sadhasivam
2021-02-03 10:19             ` Boris Brezillon
2021-02-03 10:52               ` Manivannan Sadhasivam
2021-02-03 11:24                 ` Boris Brezillon
2021-02-03 11:41                   ` Manivannan Sadhasivam
2021-02-04  8:13                     ` Miquel Raynal [this message]
2021-02-04  8:52                       ` Manivannan Sadhasivam
2021-02-04  8:59                         ` Boris Brezillon
2021-02-04  9:04                           ` Miquel Raynal
2021-02-04  9:27                             ` Boris Brezillon
2021-02-04  9:31                               ` Miquel Raynal
2021-02-04  8:59                         ` Miquel Raynal

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