MIPS noncoherent DMA cleanups

MIPS noncoherent DMA cleanups

[Christoph Hellwig]

Hi Thomas,

this series cleans up some of the mips (maybe) noncoherent support.
It also remove the need for the special <asm/dma-coherence.h> header only
provided by mips.

[PATCH 1/6] MIPS/malta: simplify plat_setup_iocoherency

[Christoph Hellwig]

Merge plat_enable_iocoherency into plat_setup_iocoherency to simplify
the code a bit.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/mips/mti-malta/malta-setup.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index e1fb8b5349447e..f3fec5a5a07c76 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -90,7 +90,7 @@ static void __init fd_activate(void)
 }
 #endif
 
-static int __init plat_enable_iocoherency(void)
+static void __init plat_setup_iocoherency(void)
 {
 	int supported = 0;
 	u32 cfg;
@@ -118,19 +118,13 @@ static int __init plat_enable_iocoherency(void)
 		/* Nothing special needs to be done to enable coherency */
 		pr_info("CMP IOCU detected\n");
 		cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
-		if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
+		if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
+			supported = 1;
+		else
 			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
-			return 0;
-		}
-		supported = 1;
 	}
-	hw_coherentio = supported;
-	return supported;
-}
 
-static void __init plat_setup_iocoherency(void)
-{
-	if (plat_enable_iocoherency()) {
+	if (supported)
 		if (coherentio == IO_COHERENCE_DISABLED)
 			pr_info("Hardware DMA cache coherency disabled\n");
 		else
@@ -141,6 +135,7 @@ static void __init plat_setup_iocoherency(void)
 		else
 			pr_info("Software DMA cache coherency enabled\n");
 	}
+	hw_coherentio = supported;
 }
 
 static void __init pci_clock_check(void)
-- 
2.29.2

[PATCH 2/6] MIPS/alchemy: factor out the DMA coherent setup

[Christoph Hellwig]

Factor out a alchemy_dma_coherent helper that determines if the platform
is DMA coherent.  Also stop initializing the hw_coherentio variable, given
that is only ever set to a non-zero value by the malta setup code.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/mips/alchemy/common/setup.c | 33 ++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 0f60efe0481ecc..c2da68e7984450 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -37,6 +37,23 @@
 extern void __init board_setup(void);
 extern void __init alchemy_set_lpj(void);
 
+static bool alchemy_dma_coherent(void)
+{
+	switch (alchemy_get_cputype()) {
+	case ALCHEMY_CPU_AU1000:
+	case ALCHEMY_CPU_AU1500:
+	case ALCHEMY_CPU_AU1100:
+		return false;
+	case ALCHEMY_CPU_AU1200:
+		/* Au1200 AB USB does not support coherent memory */
+		if ((read_c0_prid() & PRID_REV_MASK) == 0)
+			return false;
+		return true;
+	default:
+		return true;
+	}
+}
+
 void __init plat_mem_setup(void)
 {
 	alchemy_set_lpj();
@@ -48,20 +65,8 @@ void __init plat_mem_setup(void)
 		/* Clear to obtain best system bus performance */
 		clear_c0_config(1 << 19); /* Clear Config[OD] */
 
-	hw_coherentio = 0;
-	coherentio = IO_COHERENCE_ENABLED;
-	switch (alchemy_get_cputype()) {
-	case ALCHEMY_CPU_AU1000:
-	case ALCHEMY_CPU_AU1500:
-	case ALCHEMY_CPU_AU1100:
-		coherentio = IO_COHERENCE_DISABLED;
-		break;
-	case ALCHEMY_CPU_AU1200:
-		/* Au1200 AB USB does not support coherent memory */
-		if (0 == (read_c0_prid() & PRID_REV_MASK))
-			coherentio = IO_COHERENCE_DISABLED;
-		break;
-	}
+	coherentio = alchemy_dma_coherent() ?
+		IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED;
 
 	board_setup();	/* board specific setup */
 
-- 
2.29.2

[PATCH 3/6] MIPS: move the {no,}nocoherentio options to the malta setup code

[Christoph Hellwig]

There are only two MIPS platforms that are conditionally DMA coherent.
Of those alchemcy forces the coherentcy base on the platform, while
malta allows a mix of hardware defaults and manual overrides.  Move the
command line options for these overrides to the malta setup code, as
they can't have an effect for alchemy.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/mips/kernel/setup.c          | 16 ----------------
 arch/mips/mti-malta/malta-setup.c | 16 ++++++++++++++++
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 7e1f8e2774373d..8e205a4e18c27b 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -811,20 +811,4 @@ arch_initcall(debugfs_mips);
 enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
 EXPORT_SYMBOL_GPL(coherentio);
 int hw_coherentio;	/* Actual hardware supported DMA coherency setting. */
-
-static int __init setcoherentio(char *str)
-{
-	coherentio = IO_COHERENCE_ENABLED;
-	pr_info("Hardware DMA cache coherency (command line)\n");
-	return 0;
-}
-early_param("coherentio", setcoherentio);
-
-static int __init setnocoherentio(char *str)
-{
-	coherentio = IO_COHERENCE_DISABLED;
-	pr_info("Software DMA cache coherency (command line)\n");
-	return 0;
-}
-early_param("nocoherentio", setnocoherentio);
 #endif
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index f3fec5a5a07c76..33449a2692c3a3 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -90,6 +90,22 @@ static void __init fd_activate(void)
 }
 #endif
 
+static int __init setcoherentio(char *str)
+{
+	coherentio = IO_COHERENCE_ENABLED;
+	pr_info("Hardware DMA cache coherency (command line)\n");
+	return 0;
+}
+early_param("coherentio", setcoherentio);
+
+static int __init setnocoherentio(char *str)
+{
+	coherentio = IO_COHERENCE_DISABLED;
+	pr_info("Software DMA cache coherency (command line)\n");
+	return 0;
+}
+early_param("nocoherentio", setnocoherentio);
+
 static void __init plat_setup_iocoherency(void)
 {
 	int supported = 0;
-- 
2.29.2

[PATCH 4/6] MIPS: refactor the maybe coherent DMA indicators

[Christoph Hellwig]

Replace the global coherentio enum, and the hw_coherentio (fake) boolean
variables with a single boolean dma_default_coherent flag.  Only the
malta setup code needs two additional local boolean variables to
preserved the command line overrides.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/mips/alchemy/common/setup.c      |  3 +--
 arch/mips/include/asm/dma-coherence.h | 24 ++++--------------------
 arch/mips/kernel/setup.c              |  8 +++-----
 arch/mips/mm/c-r4k.c                  |  8 ++------
 arch/mips/mti-malta/malta-setup.c     | 24 ++++++++++++++----------
 arch/mips/pci/pci-alchemy.c           |  5 ++---
 6 files changed, 26 insertions(+), 46 deletions(-)

diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index c2da68e7984450..39e5b9cd882b10 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -65,8 +65,7 @@ void __init plat_mem_setup(void)
 		/* Clear to obtain best system bus performance */
 		clear_c0_config(1 << 19); /* Clear Config[OD] */
 
-	coherentio = alchemy_dma_coherent() ?
-		IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED;
+	dma_default_coherent = alchemy_dma_coherent();
 
 	board_setup();	/* board specific setup */
 
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index 5eaa1fcc878a88..846c5ade30d12d 100644
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -9,30 +9,14 @@
 #ifndef __ASM_DMA_COHERENCE_H
 #define __ASM_DMA_COHERENCE_H
 
-enum coherent_io_user_state {
-	IO_COHERENCE_DEFAULT,
-	IO_COHERENCE_ENABLED,
-	IO_COHERENCE_DISABLED,
-};
-
-#if defined(CONFIG_DMA_PERDEV_COHERENT)
-/* Don't provide (hw_)coherentio to avoid misuse */
-#elif defined(CONFIG_DMA_MAYBE_COHERENT)
-extern enum coherent_io_user_state coherentio;
-extern int hw_coherentio;
-
+#ifdef CONFIG_DMA_MAYBE_COHERENT
+extern bool dma_default_coherent;
 static inline bool dev_is_dma_coherent(struct device *dev)
 {
-	return coherentio == IO_COHERENCE_ENABLED ||
-		(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
+	return dma_default_coherent;
 }
 #else
-#ifdef CONFIG_DMA_NONCOHERENT
-#define coherentio	IO_COHERENCE_DISABLED
-#else
-#define coherentio	IO_COHERENCE_ENABLED
+#define dma_default_coherent	(!IS_ENABLED(CONFIG_DMA_NONCOHERENT))
 #endif
-#define hw_coherentio	0
-#endif /* CONFIG_DMA_MAYBE_COHERENT */
 
 #endif
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8e205a4e18c27b..85690957525ac9 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -806,9 +806,7 @@ static int __init debugfs_mips(void)
 arch_initcall(debugfs_mips);
 #endif
 
-#ifdef CONFIG_DMA_MAYBE_COHERENT
-/* User defined DMA coherency from command line. */
-enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
-EXPORT_SYMBOL_GPL(coherentio);
-int hw_coherentio;	/* Actual hardware supported DMA coherency setting. */
+#ifdef CONFIG_DMA_NONCOHERENT
+bool dma_default_coherent;
+EXPORT_SYMBOL_GPL(dma_default_coherent);
 #endif
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 4f976d687ab007..58afbc3e4ada03 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1913,15 +1913,11 @@ void r4k_cache_init(void)
 	__local_flush_icache_user_range	= local_r4k_flush_icache_user_range;
 
 #ifdef CONFIG_DMA_NONCOHERENT
-#ifdef CONFIG_DMA_MAYBE_COHERENT
-	if (coherentio == IO_COHERENCE_ENABLED ||
-	    (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
+	if (dma_default_coherent) {
 		_dma_cache_wback_inv	= (void *)cache_noop;
 		_dma_cache_wback	= (void *)cache_noop;
 		_dma_cache_inv		= (void *)cache_noop;
-	} else
-#endif /* CONFIG_DMA_MAYBE_COHERENT */
-	{
+	} else {
 		_dma_cache_wback_inv	= r4k_dma_cache_wback_inv;
 		_dma_cache_wback	= r4k_dma_cache_wback_inv;
 		_dma_cache_inv		= r4k_dma_cache_inv;
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 33449a2692c3a3..e98cc977a735b2 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -90,9 +90,12 @@ static void __init fd_activate(void)
 }
 #endif
 
+static bool dma_force_coherent;
+static bool dma_force_noncoherent;
+
 static int __init setcoherentio(char *str)
 {
-	coherentio = IO_COHERENCE_ENABLED;
+	dma_force_coherent = true;
 	pr_info("Hardware DMA cache coherency (command line)\n");
 	return 0;
 }
@@ -100,7 +103,7 @@ early_param("coherentio", setcoherentio);
 
 static int __init setnocoherentio(char *str)
 {
-	coherentio = IO_COHERENCE_DISABLED;
+	dma_force_noncoherent = true;
 	pr_info("Software DMA cache coherency (command line)\n");
 	return 0;
 }
@@ -141,17 +144,18 @@ static void __init plat_setup_iocoherency(void)
 	}
 
 	if (supported)
-		if (coherentio == IO_COHERENCE_DISABLED)
+		if (dma_force_noncoherent) {
 			pr_info("Hardware DMA cache coherency disabled\n");
-		else
-			pr_info("Hardware DMA cache coherency enabled\n");
+			return;
+		}
+		pr_info("Hardware DMA cache coherency enabled\n");
+		dma_default_coherent = true;
+	} else if (dma_force_coherent) {
+		pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
+		dma_default_coherent = true;
 	} else {
-		if (coherentio == IO_COHERENCE_ENABLED)
-			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
-		else
-			pr_info("Software DMA cache coherency enabled\n");
+		pr_info("Software DMA cache coherency enabled\n");
 	}
-	hw_coherentio = supported;
 }
 
 static void __init pci_clock_check(void)
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 7285b5667568ef..54c86b40d30498 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -429,9 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev)
 	ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;
 
 	/* Au1500 revisions older than AD have borked coherent PCI */
-	if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
-	    (read_c0_prid() < 0x01030202) &&
-	    (coherentio == IO_COHERENCE_DISABLED)) {
+	if (alchemy_get_cputype() == ALCHEMY_CPU_AU1500 &&
+	    read_c0_prid() < 0x01030202 && !dma_default_coherent) {
 		val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
 		val |= PCI_CONFIG_NC;
 		__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
-- 
2.29.2

Re: [PATCH 4/6] MIPS: refactor the maybe coherent DMA indicators

[Thomas Bogendoerfer]

On Mon, Feb 08, 2021 at 03:50:22PM +0100, Christoph Hellwig wrote:
> Replace the global coherentio enum, and the hw_coherentio (fake) boolean
> variables with a single boolean dma_default_coherent flag.  Only the
> malta setup code needs two additional local boolean variables to
> preserved the command line overrides.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  arch/mips/alchemy/common/setup.c      |  3 +--
>  arch/mips/include/asm/dma-coherence.h | 24 ++++--------------------
>  arch/mips/kernel/setup.c              |  8 +++-----
>  arch/mips/mm/c-r4k.c                  |  8 ++------
>  arch/mips/mti-malta/malta-setup.c     | 24 ++++++++++++++----------
>  arch/mips/pci/pci-alchemy.c           |  5 ++---
>  6 files changed, 26 insertions(+), 46 deletions(-)
> 
> diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
> index c2da68e7984450..39e5b9cd882b10 100644
> --- a/arch/mips/alchemy/common/setup.c
> +++ b/arch/mips/alchemy/common/setup.c
> @@ -65,8 +65,7 @@ void __init plat_mem_setup(void)
>  		/* Clear to obtain best system bus performance */
>  		clear_c0_config(1 << 19); /* Clear Config[OD] */
>  
> -	coherentio = alchemy_dma_coherent() ?
> -		IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED;
> +	dma_default_coherent = alchemy_dma_coherent();
>  
>  	board_setup();	/* board specific setup */
>  
> diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
> index 5eaa1fcc878a88..846c5ade30d12d 100644
> --- a/arch/mips/include/asm/dma-coherence.h
> +++ b/arch/mips/include/asm/dma-coherence.h
> @@ -9,30 +9,14 @@
>  #ifndef __ASM_DMA_COHERENCE_H
>  #define __ASM_DMA_COHERENCE_H
>  
> -enum coherent_io_user_state {
> -	IO_COHERENCE_DEFAULT,
> -	IO_COHERENCE_ENABLED,
> -	IO_COHERENCE_DISABLED,
> -};
> -
> -#if defined(CONFIG_DMA_PERDEV_COHERENT)
> -/* Don't provide (hw_)coherentio to avoid misuse */
> -#elif defined(CONFIG_DMA_MAYBE_COHERENT)
> -extern enum coherent_io_user_state coherentio;
> -extern int hw_coherentio;
> -
> +#ifdef CONFIG_DMA_MAYBE_COHERENT
> +extern bool dma_default_coherent;
>  static inline bool dev_is_dma_coherent(struct device *dev)
>  {
> -	return coherentio == IO_COHERENCE_ENABLED ||
> -		(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
> +	return dma_default_coherent;

this breaks overriding of coherentio via command line. plat_mem_setup/
plat_setup_iocoherency is called before earlyparams are handled. So
changing coherentio after that doesn't have any effect.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH 4/6] MIPS: refactor the maybe coherent DMA indicators

[Christoph Hellwig]

On Tue, Feb 09, 2021 at 02:12:37PM +0100, Thomas Bogendoerfer wrote:
> > +#ifdef CONFIG_DMA_MAYBE_COHERENT
> > +extern bool dma_default_coherent;
> >  static inline bool dev_is_dma_coherent(struct device *dev)
> >  {
> > -	return coherentio == IO_COHERENCE_ENABLED ||
> > -		(coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
> > +	return dma_default_coherent;
> 
> this breaks overriding of coherentio via command line. plat_mem_setup/
> plat_setup_iocoherency is called before earlyparams are handled. So
> changing coherentio after that doesn't have any effect.

Hmm.  In that case a manual override does actually work for alchemy,
as that initializes coherentio from plat_mem_setup().  But the
elaborate sanity checking that malta performs in plat_setup_iocoherency
is rather pointless then, as coherentio will always be set to
IO_COHERENCE_DISABLED at this point.

[PATCH 5/6] driver core: lift dma_default_coherent into common code

[Christoph Hellwig]

Lift the dma_default_coherent variable from the mips architecture code
to the driver core.  This allows an architecture to sdefault all device
to be DMA coherent at run time, even if the kernel is build with support
for DMA noncoherent device.  By allowing device_initialize to ѕet the
->dma_coherent field to this default the amount of arch hooks required
for this behavior can be greatly reduced.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/mips/Kconfig                     |  9 ++-------
 arch/mips/alchemy/common/setup.c      |  2 +-
 arch/mips/include/asm/dma-coherence.h | 22 ----------------------
 arch/mips/kernel/setup.c              |  6 ------
 arch/mips/mm/c-r4k.c                  |  2 +-
 arch/mips/mm/dma-noncoherent.c        |  1 -
 arch/mips/mti-malta/malta-setup.c     |  4 ++--
 arch/mips/pci/pci-alchemy.c           |  2 +-
 arch/mips/pistachio/init.c            |  1 -
 drivers/base/core.c                   |  6 ++++++
 include/linux/dma-map-ops.h           |  5 ++---
 kernel/dma/Kconfig                    |  3 ---
 kernel/dma/mapping.c                  |  2 ++
 13 files changed, 17 insertions(+), 48 deletions(-)
 delete mode 100644 arch/mips/include/asm/dma-coherence.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0a17bedf4f0dba..1f1603a08a6d2d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -181,7 +181,7 @@ config MIPS_ALCHEMY
 	select CEVT_R4K
 	select CSRC_R4K
 	select IRQ_MIPS_CPU
-	select DMA_MAYBE_COHERENT	# Au1000,1500,1100 aren't, rest is
+	select DMA_NONCOHERENT		# Au1000,1500,1100 aren't, rest is
 	select MIPS_FIXUP_BIGPHYS_ADDR if PCI
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL
@@ -546,7 +546,7 @@ config MIPS_MALTA
 	select CLKSRC_MIPS_GIC
 	select COMMON_CLK
 	select CSRC_R4K
-	select DMA_MAYBE_COHERENT
+	select DMA_NONCOHERENT
 	select GENERIC_ISA_DMA
 	select HAVE_PCSPKR_PLATFORM
 	select HAVE_PCI
@@ -1127,11 +1127,6 @@ config FW_CFE
 config ARCH_SUPPORTS_UPROBES
 	bool
 
-config DMA_MAYBE_COHERENT
-	select ARCH_HAS_DMA_COHERENCE_H
-	select DMA_NONCOHERENT
-	bool
-
 config DMA_PERDEV_COHERENT
 	bool
 	select ARCH_HAS_SETUP_DMA_OPS
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 39e5b9cd882b10..2388d68786f4a7 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -28,8 +28,8 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/mm.h>
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
 
-#include <asm/dma-coherence.h>
 #include <asm/mipsregs.h>
 
 #include <au1000.h>
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
deleted file mode 100644
index 846c5ade30d12d..00000000000000
--- a/arch/mips/include/asm/dma-coherence.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
- *
- */
-#ifndef __ASM_DMA_COHERENCE_H
-#define __ASM_DMA_COHERENCE_H
-
-#ifdef CONFIG_DMA_MAYBE_COHERENT
-extern bool dma_default_coherent;
-static inline bool dev_is_dma_coherent(struct device *dev)
-{
-	return dma_default_coherent;
-}
-#else
-#define dma_default_coherent	(!IS_ENABLED(CONFIG_DMA_NONCOHERENT))
-#endif
-
-#endif
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 85690957525ac9..d95f195dddcb36 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -37,7 +37,6 @@
 #include <asm/cdmm.h>
 #include <asm/cpu.h>
 #include <asm/debug.h>
-#include <asm/dma-coherence.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp-ops.h>
@@ -805,8 +804,3 @@ static int __init debugfs_mips(void)
 }
 arch_initcall(debugfs_mips);
 #endif
-
-#ifdef CONFIG_DMA_NONCOHERENT
-bool dma_default_coherent;
-EXPORT_SYMBOL_GPL(dma_default_coherent);
-#endif
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 58afbc3e4ada03..3c4a50e12cebd4 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/export.h>
 #include <linux/bitops.h>
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
 
 #include <asm/bcache.h>
 #include <asm/bootinfo.h>
@@ -35,7 +36,6 @@
 #include <asm/war.h>
 #include <asm/cacheflush.h> /* for run_uncached() */
 #include <asm/traps.h>
-#include <asm/dma-coherence.h>
 #include <asm/mips-cps.h>
 
 /*
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 38d3d9143b47fb..90b562753eb892 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -10,7 +10,6 @@
 
 #include <asm/cache.h>
 #include <asm/cpu-type.h>
-#include <asm/dma-coherence.h>
 #include <asm/io.h>
 
 /*
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index e98cc977a735b2..f8c9663e7faa10 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -13,8 +13,8 @@
 #include <linux/pci.h>
 #include <linux/screen_info.h>
 #include <linux/time.h>
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
 
-#include <asm/dma-coherence.h>
 #include <asm/fw/fw.h>
 #include <asm/mips-cps.h>
 #include <asm/mips-boards/generic.h>
@@ -143,7 +143,7 @@ static void __init plat_setup_iocoherency(void)
 			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
 	}
 
-	if (supported)
+	if (supported) {
 		if (dma_force_noncoherent) {
 			pr_info("Hardware DMA cache coherency disabled\n");
 			return;
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 54c86b40d30498..1c722dd0c1302d 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -17,8 +17,8 @@
 #include <linux/init.h>
 #include <linux/syscore_ops.h>
 #include <linux/vmalloc.h>
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
 
-#include <asm/dma-coherence.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/tlbmisc.h>
 
diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c
index 558995ed6fe886..7d3057e586d277 100644
--- a/arch/mips/pistachio/init.c
+++ b/arch/mips/pistachio/init.c
@@ -13,7 +13,6 @@
 #include <linux/of_fdt.h>
 
 #include <asm/cacheflush.h>
-#include <asm/dma-coherence.h>
 #include <asm/fw/fw.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-cps.h>
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 6eb4c7a904c560..7c0406e675e98f 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -28,6 +28,7 @@
 #include <linux/sched/signal.h>
 #include <linux/sched/mm.h>
 #include <linux/sysfs.h>
+#include <linux/dma-map-ops.h> /* for dma_default_coherent */
 
 #include "base.h"
 #include "power/power.h"
@@ -2603,6 +2604,11 @@ void device_initialize(struct device *dev)
 	INIT_LIST_HEAD(&dev->links.suppliers);
 	INIT_LIST_HEAD(&dev->links.defer_sync);
 	dev->links.status = DL_DEV_NO_DRIVER;
+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
+    defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
+    defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
+	dev->dma_coherent = dma_default_coherent;
+#endif
 }
 EXPORT_SYMBOL_GPL(device_initialize);
 
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index 70fcd0f610ea48..1e98b8c1e055a9 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -229,11 +229,10 @@ bool dma_free_from_pool(struct device *dev, void *start, size_t size);
 int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
 		dma_addr_t dma_start, u64 size);
 
-#ifdef CONFIG_ARCH_HAS_DMA_COHERENCE_H
-#include <asm/dma-coherence.h>
-#elif defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
+#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
 	defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
 	defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
+extern bool dma_default_coherent;
 static inline bool dev_is_dma_coherent(struct device *dev)
 {
 	return dev->dma_coherent;
diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig
index 479fc145acfc16..77b4055087430c 100644
--- a/kernel/dma/Kconfig
+++ b/kernel/dma/Kconfig
@@ -33,9 +33,6 @@ config NEED_DMA_MAP_STATE
 config ARCH_DMA_ADDR_T_64BIT
 	def_bool 64BIT || PHYS_ADDR_T_64BIT
 
-config ARCH_HAS_DMA_COHERENCE_H
-	bool
-
 config ARCH_HAS_DMA_SET_MASK
 	bool
 
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index f87a89d086544b..84de6b1c5fab49 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -16,6 +16,8 @@
 #include "debug.h"
 #include "direct.h"
 
+bool dma_default_coherent;
+
 /*
  * Managed DMA API
  */
-- 
2.29.2

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Greg Kroah-Hartman]

On Mon, Feb 08, 2021 at 03:50:23PM +0100, Christoph Hellwig wrote:
> Lift the dma_default_coherent variable from the mips architecture code
> to the driver core.  This allows an architecture to sdefault all device
> to be DMA coherent at run time, even if the kernel is build with support
> for DMA noncoherent device.  By allowing device_initialize to ѕet the
> ->dma_coherent field to this default the amount of arch hooks required
> for this behavior can be greatly reduced.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Maciej W. Rozycki]

On Mon, 8 Feb 2021, Christoph Hellwig wrote:

> diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
> index e98cc977a735b2..f8c9663e7faa10 100644
> --- a/arch/mips/mti-malta/malta-setup.c
> +++ b/arch/mips/mti-malta/malta-setup.c
> @@ -143,7 +143,7 @@ static void __init plat_setup_iocoherency(void)
>  			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
>  	}
>  
> -	if (supported)
> +	if (supported) {
>  		if (dma_force_noncoherent) {
>  			pr_info("Hardware DMA cache coherency disabled\n");
>  			return;

 I think this has to go with 1/6; otherwise compilation breaks between 
then and now AFAICT.

 Do you need to have this verified anyhow?  I only have a non-coherent 5Kc 
Malta though.

  Maciej

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Christoph Hellwig]

On Mon, Feb 08, 2021 at 04:57:33PM +0100, Maciej W. Rozycki wrote:
> > diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
> > index e98cc977a735b2..f8c9663e7faa10 100644
> > --- a/arch/mips/mti-malta/malta-setup.c
> > +++ b/arch/mips/mti-malta/malta-setup.c
> > @@ -143,7 +143,7 @@ static void __init plat_setup_iocoherency(void)
> >  			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
> >  	}
> >  
> > -	if (supported)
> > +	if (supported) {
> >  		if (dma_force_noncoherent) {
> >  			pr_info("Hardware DMA cache coherency disabled\n");
> >  			return;
> 
>  I think this has to go with 1/6; otherwise compilation breaks between 
> then and now AFAICT.

Indeed.

>  Do you need to have this verified anyhow?  I only have a non-coherent 5Kc 
> Malta though.

If you get a chance to test this logic, that would be great.

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Maciej W. Rozycki]

On Mon, 8 Feb 2021, Christoph Hellwig wrote:

> >  Do you need to have this verified anyhow?  I only have a non-coherent 5Kc 
> > Malta though.
> 
> If you get a chance to test this logic, that would be great.

 I'll try to give it a hit in the next few days then.  Installed in my 
Malta I have a DEFPA, which is about as serious a DMA user as a piece of 
classic PCI hardware could be.  I need to debug the issue of another DEFPA 
not working with my POWER9 system, possibly due to an IOMMU handling bug 
(hopefully not broken host hardware), so I'll take the opportunity and do 
it all at once.

  Maciej

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Maciej W. Rozycki]

On Tue, 9 Feb 2021, Maciej W. Rozycki wrote:

> > >  Do you need to have this verified anyhow?  I only have a non-coherent 5Kc 
> > > Malta though.
> > 
> > If you get a chance to test this logic, that would be great.
> 
>  I'll try to give it a hit in the next few days then.  Installed in my 
> Malta I have a DEFPA, which is about as serious a DMA user as a piece of 
> classic PCI hardware could be.  I need to debug the issue of another DEFPA 
> not working with my POWER9 system, possibly due to an IOMMU handling bug 
> (hopefully not broken host hardware), so I'll take the opportunity and do 
> it all at once.

 FYI still working on it.  The POWER9 issue turned out to be a combination 
of a driver configuration issue with the distribution caused by a chain of 
historical events leading to the use of PCI I/O bus commands not supported 
by the PHB PCIe host bridge and a bad solder joint with the adapter's main 
PDQ IC on a 20+ years old brand new card.

 I hope to have the adapter properly fixed soon and I'll look at the Malta 
side now, possibly using the old server whose DEFPA has worked flawlessly 
for some 20 years now.  I have planned to use the interface to supply NFS 
root, which I think should be enough of a stress test.

 Patches will follow sometime too for the driver's configuration issue, a 
nonsense in 2021 I should have long addressed, and for resource handling 
which I think should explicitly fail port I/O claims on a system that does 
not support port I/O at all and should not allow this:

# cat /proc/ioports
00000000-ffffffffffffffff : 0031:02:04.0
# 

to happen.

  Maciej

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Maciej W. Rozycki]

On Mon, 15 Feb 2021, Maciej W. Rozycki wrote:

>  I hope to have the adapter properly fixed soon and I'll look at the Malta 
> side now, possibly using the old server whose DEFPA has worked flawlessly 
> for some 20 years now.  I have planned to use the interface to supply NFS 
> root, which I think should be enough of a stress test.

 Card reworked now and network wired, so using the new server actually.  
I haven't booted Linux on my Malta for a while now, but it turns out to 
work just fine, and your patch set does not regress it booting multi-user 
NFS-rooted over FDDI.

 I note however that the system does not reboot properly:

sd 0:0:0:0: [sda] Synchronizing SCSI cache
reboot: Restarting system
Reboot failed -- System halted

which is a regression, and also the MMIO-mapped discrete CBUS UART (ttyS2) 
does not sign in anymore either:

Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
printk: console [ttyS0] disabled
serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
printk: console [ttyS0] enabled
printk: console [ttyS0] enabled
printk: bootconsole [uart8250] disabled
printk: bootconsole [uart8250] disabled
serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A

while long ago:

Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
ttyS28 at 0x03f8 (irq = 4) is a 16550A
ttyS29 at 0x02f8 (irq = 3) is a 16550A
ttyS30 at 0x0000 (irq = 20) is a 16550

(I don't know why the line numbers reported were so odd back then, but the 
standard character device major:minor numbers for ttyS0-2 just worked), so 
there's probably something wrong with platform device registration.  ISTR 
using the CBUS UART as a console device at one point too.

  Maciej

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Christoph Hellwig]

On Sun, Feb 21, 2021 at 04:32:38AM +0100, Maciej W. Rozycki wrote:
> I haven't booted Linux on my Malta for a while now, but it turns out to 
> work just fine, and your patch set does not regress it booting multi-user 
> NFS-rooted over FDDI.
> 
>  I note however that the system does not reboot properly:
> 
> sd 0:0:0:0: [sda] Synchronizing SCSI cache
> reboot: Restarting system
> Reboot failed -- System halted
> 
> which is a regression, and also the MMIO-mapped discrete CBUS UART (ttyS2) 
> does not sign in anymore either:

Do you mean a regression with this series, or just compared to when you
last tested?

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Maciej W. Rozycki]

On Mon, 22 Feb 2021, Christoph Hellwig wrote:

> > I haven't booted Linux on my Malta for a while now, but it turns out to 
> > work just fine, and your patch set does not regress it booting multi-user 
> > NFS-rooted over FDDI.
> > 
> >  I note however that the system does not reboot properly:
> > 
> > sd 0:0:0:0: [sda] Synchronizing SCSI cache
> > reboot: Restarting system
> > Reboot failed -- System halted
> > 
> > which is a regression, and also the MMIO-mapped discrete CBUS UART (ttyS2) 
> > does not sign in anymore either:
> 
> Do you mean a regression with this series, or just compared to when you
> last tested?

 When last tested.  Years ago, so nothing for you to be concerned.  I'll 
look into it sometime unless someone beats me to.  Don't hold your breath 
though.  Sorry to be unclear.

  Maciej

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Maciej W. Rozycki]

On Mon, 22 Feb 2021, Maciej W. Rozycki wrote:

> > > I haven't booted Linux on my Malta for a while now, but it turns out to 
> > > work just fine, and your patch set does not regress it booting multi-user 
> > > NFS-rooted over FDDI.
> > > 
> > >  I note however that the system does not reboot properly:
> > > 
> > > sd 0:0:0:0: [sda] Synchronizing SCSI cache
> > > reboot: Restarting system
> > > Reboot failed -- System halted
> > > 
> > > which is a regression, and also the MMIO-mapped discrete CBUS UART (ttyS2) 
> > > does not sign in anymore either:
> > 
> > Do you mean a regression with this series, or just compared to when you
> > last tested?
> 
>  When last tested.  Years ago, so nothing for you to be concerned.  I'll 
> look into it sometime unless someone beats me to.  Don't hold your breath 
> though.  Sorry to be unclear.

 For the record, Malta reboot requires:

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y

to work these days, which wasn't picked automatically on an older config 
regeneration for me.  Sorry for the noise then, although ISTM that these 
would better be picked up automatically by reverse dependencies.  What's 
the point of omitting reboot support?

 Still looking into the CBUS UART issue.

  Maciej

Re: [PATCH 5/6] driver core: lift dma_default_coherent into common code

[Thomas Bogendoerfer]

On Mon, Feb 08, 2021 at 03:50:23PM +0100, Christoph Hellwig wrote:
> Lift the dma_default_coherent variable from the mips architecture code
> to the driver core.  This allows an architecture to sdefault all device
> to be DMA coherent at run time, even if the kernel is build with support
> for DMA noncoherent device.  By allowing device_initialize to ѕet the
> ->dma_coherent field to this default the amount of arch hooks required
> for this behavior can be greatly reduced.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> [..]
> @@ -143,7 +143,7 @@ static void __init plat_setup_iocoherency(void)
>  			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
>  	}
>  
> -	if (supported)
> +	if (supported) {
>  		if (dma_force_noncoherent) {
>  			pr_info("Hardware DMA cache coherency disabled\n");
>  			return;

this hunk needs to be in patch 1, otherwise it's not compilable

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

[PATCH 6/6] MIPS: remove CONFIG_DMA_PERDEV_COHERENT

[Christoph Hellwig]

Just select DMA_NONCOHERENT and ARCH_HAS_SETUP_DMA_OPS from the
MIPS_GENERIC platform instead.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/mips/Kconfig              | 8 ++------
 arch/mips/mm/dma-noncoherent.c | 2 +-
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1f1603a08a6d2d..fae02b0b9c599a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -123,6 +123,7 @@ choice
 
 config MIPS_GENERIC_KERNEL
 	bool "Generic board-agnostic MIPS kernel"
+	select ARCH_HAS_SETUP_DMA_OPS
 	select MIPS_GENERIC
 	select BOOT_RAW
 	select BUILTIN_DTB
@@ -132,7 +133,7 @@ config MIPS_GENERIC_KERNEL
 	select CPU_MIPSR2_IRQ_EI
 	select CPU_MIPSR2_IRQ_VI
 	select CSRC_R4K
-	select DMA_PERDEV_COHERENT
+	select DMA_NONCOHERENT
 	select HAVE_PCI
 	select IRQ_MIPS_CPU
 	select MIPS_AUTO_PFN_OFFSET
@@ -1127,11 +1128,6 @@ config FW_CFE
 config ARCH_SUPPORTS_UPROBES
 	bool
 
-config DMA_PERDEV_COHERENT
-	bool
-	select ARCH_HAS_SETUP_DMA_OPS
-	select DMA_NONCOHERENT
-
 config DMA_NONCOHERENT
 	bool
 	#
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 90b562753eb892..212f3ce75a6bd3 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -135,7 +135,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 }
 #endif
 
-#ifdef CONFIG_DMA_PERDEV_COHERENT
+#ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS
 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 		const struct iommu_ops *iommu, bool coherent)
 {
-- 
2.29.2

Re: [PATCH 6/6] MIPS: remove CONFIG_DMA_PERDEV_COHERENT

[Huacai Chen]

Reviewed-by: Huacai Chen <chenhuacai@kernel.org>

On Mon, Feb 8, 2021 at 10:51 PM Christoph Hellwig <hch@lst.de> wrote:
>
> Just select DMA_NONCOHERENT and ARCH_HAS_SETUP_DMA_OPS from the
> MIPS_GENERIC platform instead.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  arch/mips/Kconfig              | 8 ++------
>  arch/mips/mm/dma-noncoherent.c | 2 +-
>  2 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 1f1603a08a6d2d..fae02b0b9c599a 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -123,6 +123,7 @@ choice
>
>  config MIPS_GENERIC_KERNEL
>         bool "Generic board-agnostic MIPS kernel"
> +       select ARCH_HAS_SETUP_DMA_OPS
>         select MIPS_GENERIC
>         select BOOT_RAW
>         select BUILTIN_DTB
> @@ -132,7 +133,7 @@ config MIPS_GENERIC_KERNEL
>         select CPU_MIPSR2_IRQ_EI
>         select CPU_MIPSR2_IRQ_VI
>         select CSRC_R4K
> -       select DMA_PERDEV_COHERENT
> +       select DMA_NONCOHERENT
>         select HAVE_PCI
>         select IRQ_MIPS_CPU
>         select MIPS_AUTO_PFN_OFFSET
> @@ -1127,11 +1128,6 @@ config FW_CFE
>  config ARCH_SUPPORTS_UPROBES
>         bool
>
> -config DMA_PERDEV_COHERENT
> -       bool
> -       select ARCH_HAS_SETUP_DMA_OPS
> -       select DMA_NONCOHERENT
> -
>  config DMA_NONCOHERENT
>         bool
>         #
> diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
> index 90b562753eb892..212f3ce75a6bd3 100644
> --- a/arch/mips/mm/dma-noncoherent.c
> +++ b/arch/mips/mm/dma-noncoherent.c
> @@ -135,7 +135,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
>  }
>  #endif
>
> -#ifdef CONFIG_DMA_PERDEV_COHERENT
> +#ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS
>  void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
>                 const struct iommu_ops *iommu, bool coherent)
>  {
> --
> 2.29.2
>

MIPS noncoherent DMA cleanups v2

[Christoph Hellwig]

Hi Thomas,

this series cleans up some of the mips (maybe) noncoherent support.
It also remove the need for the special <asm/dma-coherence.h> header only
provided by mips.

Changes since v1:
 - fix a bisection issue due to a missing brace
 - simplify the parameter parsing given that it happens after
   plat_mem_init

[PATCH 1/6] MIPS/malta: simplify plat_setup_iocoherency

[Christoph Hellwig]

Given that plat_mem_setup runs before earlyparams are handled and malta
selects CONFIG_DMA_MAYBE_COHERENT, coherentio can only be set to
IO_COHERENCE_DEFAULT at this point.  So remove the checking for other
options and merge plat_enable_iocoherency into plat_setup_iocoherency
to simplify the code a bit.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/mips/mti-malta/malta-setup.c | 32 +++++++++----------------------
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index e1fb8b5349447e..4caff9e3b45637 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -90,16 +90,15 @@ static void __init fd_activate(void)
 }
 #endif
 
-static int __init plat_enable_iocoherency(void)
+static void __init plat_setup_iocoherency(void)
 {
-	int supported = 0;
 	u32 cfg;
 
 	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
 		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
 			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
 			pr_info("Enabled Bonito CPU coherency\n");
-			supported = 1;
+			hw_coherentio = 1;
 		}
 		if (strstr(fw_getcmdline(), "iobcuncached")) {
 			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
@@ -118,29 +117,16 @@ static int __init plat_enable_iocoherency(void)
 		/* Nothing special needs to be done to enable coherency */
 		pr_info("CMP IOCU detected\n");
 		cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
-		if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
+		if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
+			hw_coherentio = 1;
+		else
 			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
-			return 0;
-		}
-		supported = 1;
 	}
-	hw_coherentio = supported;
-	return supported;
-}
 
-static void __init plat_setup_iocoherency(void)
-{
-	if (plat_enable_iocoherency()) {
-		if (coherentio == IO_COHERENCE_DISABLED)
-			pr_info("Hardware DMA cache coherency disabled\n");
-		else
-			pr_info("Hardware DMA cache coherency enabled\n");
-	} else {
-		if (coherentio == IO_COHERENCE_ENABLED)
-			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
-		else
-			pr_info("Software DMA cache coherency enabled\n");
-	}
+	if (hw_coherentio)
+		pr_info("Hardware DMA cache coherency enabled\n");
+	else
+		pr_info("Software DMA cache coherency enabled\n");
 }
 
 static void __init pci_clock_check(void)
-- 
2.29.2

Re: [PATCH 1/6] MIPS/malta: simplify plat_setup_iocoherency

[Maciej W. Rozycki]

On Wed, 10 Feb 2021, Christoph Hellwig wrote:

> Given that plat_mem_setup runs before earlyparams are handled and malta
> selects CONFIG_DMA_MAYBE_COHERENT, coherentio can only be set to
> IO_COHERENCE_DEFAULT at this point.  So remove the checking for other
> options and merge plat_enable_iocoherency into plat_setup_iocoherency
> to simplify the code a bit.

Tested-by: Maciej W. Rozycki <macro@orcam.me.uk>

 FWIW,

  Maciej