From: Jonathan Marek <jonathan@marek.ca>
To: freedreno@lists.freedesktop.org
Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Jordan Crouse <jcrouse@codeaurora.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
Eric Anholt <eric@anholt.net>,
Sharat Masetty <smasetty@codeaurora.org>,
linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM
ADRENO GPU),
dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM
ADRENO GPU), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH] drm/msm: fix a6xx_gmu_clear_oob
Date: Mon, 8 Feb 2021 13:55:54 -0500 [thread overview]
Message-ID: <20210208185557.15703-1-jonathan@marek.ca> (raw)
The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing
bitshift operation.
Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 71c917f909af..91cf46f84025 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -339,7 +339,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
else
bit = a6xx_gmu_oob_bits[state].ack_new;
- gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit);
+ gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
}
/* Enable CPU control of SPTP power power collapse */
--
2.26.1
next reply other threads:[~2021-02-08 20:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-08 18:55 Jonathan Marek [this message]
2021-02-10 1:24 ` [PATCH] drm/msm: fix a6xx_gmu_clear_oob Jordan Crouse
2021-02-10 23:40 ` Eric Anholt
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