From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 204A7C433E6 for ; Wed, 10 Feb 2021 09:29:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D5E9E64E3B for ; Wed, 10 Feb 2021 09:29:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231230AbhBJJ2U (ORCPT ); Wed, 10 Feb 2021 04:28:20 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:60220 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbhBJJVd (ORCPT ); Wed, 10 Feb 2021 04:21:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1612948893; x=1644484893; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EitwlEv438Vmd9Yz8+ODUmwaJpdWozhshK4xgZMEcb8=; b=uzd6CTjUCM9yY6cqS71Y2ZtRatyVPL/fdQ6nxSH5Lv5G7jOaJcJ1FRd3 6F3kOGTSbUdNDoEOgk4uglTZfZeq37kBrz8jF269bEwHFFrrSwg9aFEyd UgwBsURNm8uQORshhBiaPrgH6YWjeHDstAChnyiQ1zgd5DuDDEExvv7V+ X173ZJc5OuaAKUpuBJ/nki5FRKarcd2gQrgC5wDUDQrCkYIx6BQ14SXQ7 WFneBE+MUhkbWk+MuUyGZAx0HJ50M0OyN0t3TBuHEPnki+mfLx2Qb45Eb lexswB6irzO3FIEutfb6qLxBBdzczCcndwllG/S1trDQTMAV2voAy3m2Q g==; IronPort-SDR: uNJO79MzmtsEIPOMimILqv/S7zXmwRGLa8qu61ploBfYutwXXKx23U5EmNj5R3hGt+Vbj61VZq W+c9WFWAPKexmr2aAasRBQdaQWup8f1NImVKcJAaaEjX2/YSQ6Ly0FmkCXwcOqCwl5f7A817vz HrXeLtIZ0vScXdKcw54I6myvRl5Ty0/EPl4HS8ObP5itbB/SmUzje1WgcyDPUBi9UCOt/nbNc/ ICylSPy9qD7ShEQueWA4EtOf9XPtyII5irbd7sHGMKFvuUe7x7zCdy0vCVChERQ7s8Ek8XaehF XMU= X-IronPort-AV: E=Sophos;i="5.81,167,1610434800"; d="scan'208";a="109186009" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Feb 2021 02:20:09 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 10 Feb 2021 02:20:08 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 10 Feb 2021 02:20:06 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , , Subject: [PATCH v5 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver Date: Wed, 10 Feb 2021 10:19:52 +0100 Message-ID: <20210210091952.2013027-4-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210091952.2013027-1-steen.hegelund@microchip.com> References: <20210210091952.2013027-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This provides reset driver support for the Microchip Sparx5 PCB134 and PCB135 reference boards. Signed-off-by: Steen Hegelund --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 380281f312d8..06ecaa9ac8aa 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -132,9 +132,12 @@ mux: mux-controller { }; }; - reset@611010008 { - compatible = "microchip,sparx5-chip-reset"; - reg = <0x6 0x11010008 0x4>; + reset: reset-controller@0 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x6 0x00000000 0xd0>, + <0x6 0x11010000 0x10000>; + reg-names = "cpu", "gcb"; + #reset-cells = <1>; }; uart0: serial@600100000 { -- 2.30.0