From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B682CC433E6 for ; Wed, 10 Feb 2021 10:33:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7415064E31 for ; Wed, 10 Feb 2021 10:33:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231316AbhBJKc7 (ORCPT ); Wed, 10 Feb 2021 05:32:59 -0500 Received: from 8bytes.org ([81.169.241.247]:55184 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230306AbhBJKWk (ORCPT ); Wed, 10 Feb 2021 05:22:40 -0500 Received: from cap.home.8bytes.org (p549adcf6.dip0.t-ipconnect.de [84.154.220.246]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by theia.8bytes.org (Postfix) with ESMTPSA id 1FBD846E; Wed, 10 Feb 2021 11:21:57 +0100 (CET) From: Joerg Roedel To: x86@kernel.org Cc: Joerg Roedel , Joerg Roedel , hpa@zytor.com, Andy Lutomirski , Dave Hansen , Peter Zijlstra , Jiri Slaby , Dan Williams , Tom Lendacky , Juergen Gross , Kees Cook , David Rientjes , Cfir Cohen , Erdem Aktas , Masami Hiramatsu , Mike Stunes , Sean Christopherson , Martin Radev , Arvind Sankar , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, virtualization@lists.linux-foundation.org Subject: [PATCH 4/7] x86/boot/compressed/64: Add 32-bit boot #VC handler Date: Wed, 10 Feb 2021 11:21:32 +0100 Message-Id: <20210210102135.30667-5-joro@8bytes.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210210102135.30667-1-joro@8bytes.org> References: <20210210102135.30667-1-joro@8bytes.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joerg Roedel Add a #VC exception handler which is used when the kernel still executes in protected mode. This boot-path already uses CPUID, which will cause #VC exceptions in an SEV-ES guest. Signed-off-by: Joerg Roedel --- arch/x86/boot/compressed/head_64.S | 6 ++ arch/x86/boot/compressed/mem_encrypt.S | 77 +++++++++++++++++++++++++- 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 8deeec78cdb4..eadaa0a082b8 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -34,6 +34,7 @@ #include #include #include +#include #include "pgtable.h" /* @@ -856,6 +857,11 @@ SYM_FUNC_START(startup32_set_idt_entry) SYM_FUNC_END(startup32_set_idt_entry) SYM_FUNC_START(startup32_load_idt) + /* #VC handler */ + leal rva(startup32_vc_handler)(%ebp), %eax + movl $X86_TRAP_VC, %edx + call startup32_set_idt_entry + /* Load IDT */ leal rva(boot32_idt)(%ebp), %eax movl %eax, rva(boot32_idt_desc+2)(%ebp) diff --git a/arch/x86/boot/compressed/mem_encrypt.S b/arch/x86/boot/compressed/mem_encrypt.S index aa561795efd1..350ecb56c7e4 100644 --- a/arch/x86/boot/compressed/mem_encrypt.S +++ b/arch/x86/boot/compressed/mem_encrypt.S @@ -67,10 +67,85 @@ SYM_FUNC_START(get_sev_encryption_bit) ret SYM_FUNC_END(get_sev_encryption_bit) +/* + * Emit code to request an CPUID register from the Hypervisor using + * the MSR-based protocol. + * + * fn: The register containing the CPUID function + * reg: Register requested + * 1 = EAX + * 2 = EBX + * 3 = ECX + * 4 = EDX + * + * Result is in EDX. Jumps to .Lfail on error + */ +.macro SEV_ES_REQ_CPUID fn:req reg:req + /* Request CPUID[%ebx].EAX */ + movl $\reg, %eax + shll $30, %eax + orl $0x00000004, %eax + movl \fn, %edx + movl $MSR_AMD64_SEV_ES_GHCB, %ecx + wrmsr + rep; vmmcall + rdmsr + /* Check response code */ + andl $0xfff, %eax + cmpl $5, %eax + jne .Lfail + /* All good */ +.endm + +SYM_CODE_START(startup32_vc_handler) + pushl %eax + pushl %ebx + pushl %ecx + pushl %edx + + /* Keep CPUID function in %ebx */ + movl %eax, %ebx + + /* Check if error-code == SVM_EXIT_CPUID */ + cmpl $0x72, 16(%esp) + jne .Lfail + + /* Request CPUID[%ebx].EAX */ + SEV_ES_REQ_CPUID fn=%ebx reg=0 + movl %edx, 12(%esp) + + /* Request CPUID[%ebx].EBX */ + SEV_ES_REQ_CPUID fn=%ebx reg=1 + movl %edx, 8(%esp) + + /* Request CPUID[%ebx].ECX */ + SEV_ES_REQ_CPUID fn=%ebx reg=2 + movl %edx, 4(%esp) + + /* Request CPUID[%ebx].EDX */ + SEV_ES_REQ_CPUID fn=%ebx reg=3 + movl %edx, (%esp) + + popl %edx + popl %ecx + popl %ebx + popl %eax + + /* Remove error code */ + addl $4, %esp + + /* Jump over CPUID instruction */ + addl $2, (%esp) + + iret +.Lfail: + hlt + jmp .Lfail +SYM_CODE_END(startup32_vc_handler) + .code64 #include "../../kernel/sev_verify_cbit.S" - SYM_FUNC_START(set_sev_encryption_mask) #ifdef CONFIG_AMD_MEM_ENCRYPT push %rbp -- 2.30.0