From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: ezequiel@collabora.com, p.zabel@pengutronix.de,
mchehab@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com, linux-imx@nxp.com,
gregkh@linuxfoundation.org, mripard@kernel.org,
paul.kocialkowski@bootlin.com, wens@csie.org,
jernej.skrabec@siol.net, krzk@kernel.org, shengjiu.wang@nxp.com,
adrian.ratiu@collabora.com, aisheng.dong@nxp.com,
peng.fan@nxp.com, Anson.Huang@nxp.com, hverkuil-cisco@xs4all.nl
Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devel@driverdev.osuosl.org,
kernel@collabora.com,
Benjamin Gaignard <benjamin.gaignard@collabora.com>
Subject: [PATCH v1 16/18] media: hantro: IMX8M: add variant for G2/HEVC codec
Date: Wed, 17 Feb 2021 09:03:04 +0100 [thread overview]
Message-ID: <20210217080306.157876-17-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210217080306.157876-1-benjamin.gaignard@collabora.com>
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
Retrieve the hardware version at init to distinguish G1 from G2.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
---
drivers/staging/media/hantro/hantro_drv.c | 1 +
drivers/staging/media/hantro/hantro_hw.h | 1 +
drivers/staging/media/hantro/imx8m_vpu_hw.c | 95 ++++++++++++++++++++-
3 files changed, 93 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index d171fb80876a..f3d35ca19eaf 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -583,6 +583,7 @@ static const struct of_device_id of_hantro_match[] = {
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
+ { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
index fbd4943ad1cd..a52aa817b2af 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -192,6 +192,7 @@ extern const struct hantro_variant rk3399_vpu_variant;
extern const struct hantro_variant rk3328_vpu_variant;
extern const struct hantro_variant rk3288_vpu_variant;
extern const struct hantro_variant imx8mq_vpu_variant;
+extern const struct hantro_variant imx8mq_vpu_g2_variant;
extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
index d5b4312b9391..d5bdfdc48e4d 100644
--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
@@ -12,6 +12,7 @@
#include "hantro.h"
#include "hantro_jpeg.h"
#include "hantro_g1_regs.h"
+#include "hantro_g2_regs.h"
static int imx8mq_runtime_resume(struct hantro_dev *vpu)
{
@@ -90,6 +91,26 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
},
};
+static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .codec_mode = HANTRO_MODE_NONE,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .codec_mode = HANTRO_MODE_HEVC_DEC,
+ .max_depth = 2,
+ .frmsize = {
+ .min_width = 48,
+ .max_width = 3840,
+ .step_width = MB_DIM,
+ .min_height = 48,
+ .max_height = 2160,
+ .step_height = MB_DIM,
+ },
+ },
+};
+
static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
{
struct hantro_dev *vpu = dev_id;
@@ -108,9 +129,42 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id)
+{
+ struct hantro_dev *vpu = dev_id;
+ enum vb2_buffer_state state;
+ u32 status;
+
+ status = vdpu_read(vpu, HEVC_REG_INTERRUPT);
+ state = (status & HEVC_REG_INTERRUPT_DEC_RDY_INT) ?
+ VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
+
+ vdpu_write(vpu, 0, HEVC_REG_INTERRUPT);
+ vdpu_write(vpu, HEVC_REG_CONFIG_DEC_CLK_GATE_E, HEVC_REG_CONFIG);
+
+ hantro_irq_done(vpu, state);
+
+ return IRQ_HANDLED;
+}
+
static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
{
- vpu->dec_base = vpu->reg_bases[0];
+ int ret;
+
+ /* Check variant version */
+ ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);
+ if (ret) {
+ dev_err(vpu->dev, "Failed to enable clocks\n");
+ return ret;
+ }
+
+ /* Make that the device has been reset before read it id */
+ ret = device_reset(vpu->dev);
+ if (ret)
+ dev_err(vpu->dev, "Failed to reset Hantro VPU\n");
+
+ vpu->core_hw_dec_rev = (vdpu_read(vpu, HEVC_REG_VERSION) >> 16) & 0xffff;
+ clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);
return 0;
}
@@ -149,17 +203,32 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = {
},
};
+static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
+ [HANTRO_MODE_HEVC_DEC] = {
+ .run = hantro_g2_hevc_dec_run,
+ .reset = imx8mq_vpu_reset,
+ .init = hantro_hevc_dec_init,
+ .exit = hantro_hevc_dec_exit,
+ },
+};
+
/*
* VPU variants.
*/
static const struct hantro_irq imx8mq_irqs[] = {
{ "g1", imx8m_vpu_g1_irq },
- { "g2", NULL /* TODO: imx8m_vpu_g2_irq */ },
};
-static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
-static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" };
+static const struct hantro_irq imx8mq_g2_irqs[] = {
+ { "g2", imx8m_vpu_g2_irq },
+};
+
+static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus"};
+static const char * const imx8mq_reg_names[] = { "g1"};
+
+static const char * const imx8mq_g2_clk_names[] = { "g1", "g2", "bus"};
+static const char * const imx8mq_g2_reg_names[] = { "g2"};
const struct hantro_variant imx8mq_vpu_variant = {
.dec_fmts = imx8m_vpu_dec_fmts,
@@ -179,3 +248,21 @@ const struct hantro_variant imx8mq_vpu_variant = {
.reg_names = imx8mq_reg_names,
.num_regs = ARRAY_SIZE(imx8mq_reg_names)
};
+
+const struct hantro_variant imx8mq_vpu_g2_variant = {
+ .dec_offset = 0x0,
+ .dec_fmts = imx8m_vpu_g2_dec_fmts,
+ .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts),
+ .postproc_fmts = imx8m_vpu_postproc_fmts,
+ .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
+ .codec = HANTRO_HEVC_DECODER,
+ .codec_ops = imx8mq_vpu_g2_codec_ops,
+ .init = imx8mq_vpu_hw_init,
+ .runtime_resume = imx8mq_runtime_resume,
+ .irqs = imx8mq_g2_irqs,
+ .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs),
+ .clk_names = imx8mq_g2_clk_names,
+ .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names),
+ .reg_names = imx8mq_g2_reg_names,
+ .num_regs = ARRAY_SIZE(imx8mq_g2_reg_names),
+};
--
2.25.1
next prev parent reply other threads:[~2021-02-17 8:10 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-17 8:02 [PATCH v1 00/18] Add HANTRO G2/HEVC decoder support for IMX8MQ Benjamin Gaignard
2021-02-17 8:02 ` [PATCH v1 01/18] include: media: hevc: Add scaling and decode params controls Benjamin Gaignard
2021-02-17 8:02 ` [PATCH v1 02/18] media: hantro: Define HEVC codec profiles and supported features Benjamin Gaignard
2021-02-17 19:31 ` Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 03/18] arm64: dts: imx8mq-evk: add reserve memory node for CMA region Benjamin Gaignard
2021-02-17 19:39 ` Ezequiel Garcia
2021-02-18 10:15 ` Lucas Stach
2021-02-18 10:45 ` Dan Carpenter
2021-02-17 8:02 ` [PATCH v1 04/18] media: hevc: add structures for hevc codec Benjamin Gaignard
2021-02-17 19:54 ` Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 05/18] media: controls: Add control for HEVC codec Benjamin Gaignard
2021-02-17 19:58 ` Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 06/18] media: hantro: Make sure that ctx->codex_ops is set Benjamin Gaignard
2021-02-17 20:11 ` Ezequiel Garcia
2021-02-18 10:53 ` Dan Carpenter
2021-02-17 8:02 ` [PATCH v1 07/18] media: hantro: Add a field to distinguish the hardware versions Benjamin Gaignard
2021-02-17 20:15 ` Ezequiel Garcia
2021-02-18 10:55 ` Dan Carpenter
2021-02-17 8:02 ` [PATCH v1 08/18] media: hantro: Add HEVC structures Benjamin Gaignard
2021-02-17 8:02 ` [PATCH v1 09/18] media: hantro: move hantro_needs_postproc function Benjamin Gaignard
2021-02-18 10:59 ` Dan Carpenter
2021-02-17 8:02 ` [PATCH v1 10/18] media: hantro: Add helper functions for buffer information Benjamin Gaignard
2021-02-17 20:31 ` Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 11/18] media: hantro: Add helper function for auxiliary buffers allocation Benjamin Gaignard
2021-02-17 20:42 ` Ezequiel Garcia
2021-02-18 14:51 ` Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 12/18] media: uapi: Add a control for HANTRO driver Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 13/18] media: hantro: Introduce G2/HEVC decoder Benjamin Gaignard
2021-02-17 20:45 ` Ezequiel Garcia
2021-02-18 10:43 ` Benjamin Gaignard
2021-02-18 11:47 ` Dan Carpenter
2021-02-17 8:03 ` [PATCH v1 14/18] media: hantro: add G2 support to postproc Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 15/18] media: hantro: handle V4L2_PIX_FMT_HEVC_SLICE control Benjamin Gaignard
2021-02-17 20:13 ` Ezequiel Garcia
2021-02-17 8:03 ` Benjamin Gaignard [this message]
2021-02-17 8:03 ` [PATCH v1 17/18] dt-bindings: media: nxp,imx8mq-vpu: Update bindings Benjamin Gaignard
2021-02-17 22:48 ` Rob Herring
2021-02-18 14:48 ` Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 18/18] arm64: dts: imx8mq: Add node to G2 hardware Benjamin Gaignard
2021-02-17 20:43 ` Ezequiel Garcia
2021-02-18 15:47 ` Benjamin Gaignard
2021-02-17 8:08 ` [PATCH v1 00/18] Add HANTRO G2/HEVC decoder support for IMX8MQ Greg KH
2021-02-17 8:28 ` Benjamin Gaignard
2021-02-17 8:36 ` Greg KH
2021-02-17 9:10 ` Hans Verkuil
2021-02-17 9:23 ` Greg KH
2021-02-17 8:38 ` Paul Kocialkowski
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