Re: [PATCH V0 3/6] soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC)

[kernel test robot <lkp@intel.com>]

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Hi Souradeep,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.11 next-20210216]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Souradeep-Chowdhury/Add-driver-support-for-Data-Capture-and-Compare-Engine-DCC-for-SM8150/20210217-145428
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/98f7664a4e41764c0d2111d6b17905d974aad65d
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Souradeep-Chowdhury/Add-driver-support-for-Data-Capture-and-Compare-Engine-DCC-for-SM8150/20210217-145428
        git checkout 98f7664a4e41764c0d2111d6b17905d974aad65d
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/soc/qcom/dcc.c: In function '_dcc_ll_cfg_default':
>> drivers/soc/qcom/dcc.c:360:4: warning: this 'if' clause does not guard... [-Wmisleading-indentation]
     360 |    if (ret)
         |    ^~
   drivers/soc/qcom/dcc.c:362:5: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
     362 |     cfg->sram_offset += 4;
         |     ^~~
   At top level:
   drivers/soc/qcom/dcc.c:787:12: warning: 'dcc_add_write' defined but not used [-Wunused-function]
     787 | static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
         |            ^~~~~~~~~~~~~
   drivers/soc/qcom/dcc.c:750:12: warning: 'dcc_rd_mod_wr_add' defined but not used [-Wunused-function]
     750 | static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
         |            ^~~~~~~~~~~~~~~~~
   drivers/soc/qcom/dcc.c:733:12: warning: 'dcc_add_loop' defined but not used [-Wunused-function]
     733 | static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
         |            ^~~~~~~~~~~~
   drivers/soc/qcom/dcc.c:631:12: warning: 'dcc_config_add' defined but not used [-Wunused-function]
     631 | static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
         |            ^~~~~~~~~~~~~~
   drivers/soc/qcom/dcc.c:574:12: warning: 'dcc_enable' defined but not used [-Wunused-function]
     574 | static int dcc_enable(struct dcc_drvdata *drvdata)
         |            ^~~~~~~~~~


vim +/if +360 drivers/soc/qcom/dcc.c

   338	
   339	static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
   340	struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg, u32 *pos, u32 *total_len)
   341	{
   342		int ret = 0;
   343		u32 off;
   344	
   345		cfg->addr = (entry->base >> 4) & BM(0, 27);
   346	
   347		if (entry->apb_bus)
   348			cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
   349		else
   350			cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
   351	
   352		off = entry->offset/4;
   353	
   354		*total_len += entry->len * 4;
   355	
   356		if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) {
   357			/* Check if we need to write prev link entry */
   358			if (cfg->link) {
   359				ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
 > 360				if (ret)
   361					return ret;
   362					cfg->sram_offset += 4;
   363			}
   364			dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset);
   365	
   366			/* Write address */
   367			ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
   368	
   369			if (ret)
   370				return ret;
   371	
   372			cfg->sram_offset += 4;
   373	
   374			/* Reset link and prev_off */
   375			cfg->link = 0;
   376			cfg->prev_off = 0;
   377		}
   378	
   379		if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
   380			dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n",
   381			entry->base, entry->offset);
   382			ret = -EINVAL;
   383			return ret;
   384		}
   385	
   386		if (cfg->link) {
   387			/*
   388			 * link already has one offset-length so new
   389			 * offset-length needs to be placed at
   390			 * bits [29:15]
   391			 */
   392			*pos = 15;
   393	
   394			/* Clear bits [31:16] */
   395			cfg->link &= BM(0, 14);
   396		} else {
   397			/*
   398			 * link is empty, so new offset-length needs
   399			 * to be placed at bits [15:0]
   400			 */
   401			*pos = 0;
   402			cfg->link = 1 << 15;
   403		}
   404	
   405		/* write new offset-length pair to correct position */
   406		cfg->link |= (((off-cfg->prev_off) & BM(0, 7)) | ((entry->len << 8) & BM(8, 14))) << *pos;
   407	
   408		cfg->link |= DCC_LINK_DESCRIPTOR;
   409	
   410		if (*pos) {
   411			ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
   412			if (ret)
   413				return ret;
   414			cfg->sram_offset += 4;
   415			cfg->link = 0;
   416		}
   417	
   418		cfg->prev_off  = off + entry->len - 1;
   419		cfg->prev_addr = cfg->addr;
   420		return ret;
   421	}
   422	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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