From: Bjorn Helgaas <helgaas@kernel.org>
To: "Antti Järvinen" <antti.jarvinen@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Alex Williamson <alex.williamson@redhat.com>,
Murali Karicheri <m-karicheri2@ti.com>,
Kishon Vijay Abraham I <kishon@ti.com>
Subject: Re: [PATCH] PCI: quirk for preventing bus reset on TI C667X
Date: Wed, 17 Feb 2021 15:18:17 -0600 [thread overview]
Message-ID: <20210217211817.GA914074@bjorn-Precision-5520> (raw)
In-Reply-To: <20210121235547.GA2705432@bjorn-Precision-5520>
On Thu, Jan 21, 2021 at 05:55:47PM -0600, Bjorn Helgaas wrote:
> On Tue, Jan 12, 2021 at 03:36:43PM +0000, Antti Järvinen wrote:
> > TI C667X does not support bus/hot reset.
> > See https://e2e.ti.com/support/processors/f/791/t/954382
>
> You can cite the URL as the source, but the URL will eventually become
> stale, so let's include the relevant details here directly.
Thanks for trying the experiment below. I'll look for a repost that
includes details from the URL directly in the commit log.
> From the forum, it looks like the device doesn't respond after a
> reset (config accesses return ~0). It seems somewhat surprising that
> something as basic as a reset would be completely broken. I wonder if
> we're not doing the reset correctly.
>
> It looks like we would probably be trying a Secondary Bus Reset using
> the bridge leading to the C667X. Can you confirm? Wonder if you
> could try doing what pci_reset_secondary_bus() does by hand:
>
> # BRIDGE=... # PCI address, e.g., 00:1c.0
> # C667X=...
> # setpci -s$C667X VENDOR_ID.w
> # setpci -s$BRIDGE BRIDGE_CONTROL.w # prints "val"
> # setpci -s$BRIDGE BRIDGE_CONTROL.w= # val | 0x40 (set SBR)
> # sleep 1
> # setpci -s$BRIDGE BRIDGE_CONTROL.w= # val (clear SBR)
> # sleep 1
> # setpci -s$C667X VENDOR_ID.w=0
> # setpci -s$C667X VENDOR_ID.w
>
> If we use this quirk and avoid the reset, I assume that means
> assigning the device to VMs with VFIO will leak state between VMs?
>
> > Signed-off-by: Antti Järvinen <antti.jarvinen@gmail.com>
> > ---
> > drivers/pci/quirks.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 653660e3ba9e..c8fcf24c5bd0 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -3578,6 +3578,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
> > */
> > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
> >
> > +/*
> > + * Some TI keystone C667X devices do no support bus/hot reset.
> > + * https://e2e.ti.com/support/processors/f/791/t/954382
> > + */
> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
> > +
> > static void quirk_no_pm_reset(struct pci_dev *dev)
> > {
> > /*
> > --
> > 2.17.1
> >
next prev parent reply other threads:[~2021-02-17 21:20 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 15:36 [PATCH] PCI: quirk for preventing bus reset on TI C667X Antti Järvinen
2021-01-21 23:55 ` Bjorn Helgaas
2021-01-26 11:22 ` Antti Järvinen
2021-01-29 23:49 ` Bjorn Helgaas
2021-02-17 21:18 ` Bjorn Helgaas [this message]
2021-02-28 13:53 ` [PATCH v2] " Antti Järvinen
2021-03-07 0:22 ` Krzysztof Wilczyński
2021-03-08 14:21 ` [PATCH v3] PCI: Add " Antti Järvinen
2021-03-12 21:09 ` Bjorn Helgaas
2021-03-15 10:26 ` [PATCH v4] " Antti Järvinen
2021-04-19 12:44 ` Kishon Vijay Abraham I
2021-05-27 23:07 ` Bjorn Helgaas
2021-03-15 10:45 ` [PATCH v3] " Antti Järvinen
2021-03-08 14:28 ` [PATCH v2] PCI: " Antti Järvinen
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