From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E013FC4332E for ; Thu, 18 Feb 2021 18:40:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E9D464EF9 for ; Thu, 18 Feb 2021 18:40:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233101AbhBRSjk (ORCPT ); Thu, 18 Feb 2021 13:39:40 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:14295 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233085AbhBRQQ1 (ORCPT ); Thu, 18 Feb 2021 11:16:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1613664984; x=1645200984; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V30xAsGypzCvyHxMwzLUE/9K9QPg42uq4qpA4eaiTis=; b=I9ALa+m3GP+s4k1gfXBJ/8uMSLdN8mLjBCXhlzgVm8It3F8iGFydZUSP +j89F6lt6c9kt0IECNqenQACaxqks+/binbJhdLxXZE8bqPt13IYV822X lGIen7JTONRtAC1UFpI1PqXjWs9cNAb3e4uAqgjc6hRzVyYeIB/3fLgpq wHrB6NKs0zh8zvH6KkfWAtqXWLNFwlC7eykOqiu+xR1dH4ksfLOyq4Dsu qplsxU6NCURPNzbQCfAV0QhYmS+afArHn3/1sqnr2BI6bnQMwMd7O+azt +mSVeGjAmGmGSHTGYxq8O+kONNCKrwLMsa2evJzTez45nBrIBEpjcZOu6 A==; IronPort-SDR: BgtG8KZP+4hJt7C3AX/0qLmdqdR0L6F3TZliI2IYblgReme8I3Oe1ohxeSbUzgkDshNcMN5Dwi nfTD16nOEeIpqpVhm7c8/vOJNmDUk2lw4lVNbIpMhLsfMN0tHrwL6omSfc/jCALa4hs/xwBmnq NjbtXERV5at7bZoDyM/3NxlKxOCl2E4cSd+Be9eeGq+u8xgKegVPWlVsQUByTWbBHT1oOhJf5g 1v2jAzD4XTMcFRLRuwwedCpyei1GmK7HiQJiukaT7m9TUJsX7kK187MX7e+9NTVY0/T1Tuk/50 LaI= X-IronPort-AV: E=Sophos;i="5.81,187,1610434800"; d="scan'208";a="109772705" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Feb 2021 09:15:03 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 18 Feb 2021 09:15:02 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Thu, 18 Feb 2021 09:14:59 -0700 From: Steen Hegelund To: Kishon Vijay Abraham I , Vinod Koul , "Rob Herring" , Device Tree List CC: Steen Hegelund , Alexandre Belloni , Lars Povlsen , Bjarni Jonasson , Microchip UNG Driver List , , , Rob Herring , Andrew Lunn Subject: [PATCH v15 1/4] dt-bindings: phy: Add sparx5-serdes bindings Date: Thu, 18 Feb 2021 17:14:48 +0100 Message-ID: <20210218161451.3489955-2-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210218161451.3489955-1-steen.hegelund@microchip.com> References: <20210218161451.3489955-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the Sparx5 ethernet serdes phy driver bindings. Signed-off-by: Lars Povlsen Signed-off-by: Steen Hegelund Reviewed-by: Rob Herring Reviewed-by: Andrew Lunn Reviewed-by: Alexandre Belloni --- .../bindings/phy/microchip,sparx5-serdes.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml new file mode 100644 index 000000000000..bdbdb3bbddbe --- /dev/null +++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Serdes controller + +maintainers: + - Steen Hegelund + +description: | + The Sparx5 SERDES interfaces share the same basic functionality, but + support different operating modes and line rates. + + The following list lists the SERDES features: + + * RX Adaptive Decision Feedback Equalizer (DFE) + * Programmable continuous time linear equalizer (CTLE) + * Rx variable gain control + * Rx built-in fault detector (loss-of-lock/loss-of-signal) + * Adjustable tx de-emphasis (FFE) + * Tx output amplitude control + * Supports rx eye monitor + * Multiple loopback modes + * Prbs generator and checker + * Polarity inversion control + + SERDES6G: + + The SERDES6G is a high-speed SERDES interface, which can operate at + the following data rates: + + * 100 Mbps (100BASE-FX) + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX) + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX) + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII) + + SERDES10G + + The SERDES10G is a high-speed SERDES interface, which can operate at + the following data rates: + + * 100 Mbps (100BASE-FX) + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX) + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX) + * 5 Gbps (QSGMII/USGMII) + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII) + * 10 Gbps (10G-USGMII) + * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII) + + SERDES25G + + The SERDES25G is a high-speed SERDES interface, which can operate at + the following data rates: + + * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX) + * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX) + * 5 Gbps (QSGMII/USGMII) + * 5.15625 Gbps (5GBASE-KR/5G-USXGMII) + * 10 Gbps (10G-USGMII) + * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII) + * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER) + +properties: + $nodename: + pattern: "^serdes@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-serdes + + reg: + minItems: 1 + + '#phy-cells': + const: 1 + description: | + - The main serdes input port + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - '#phy-cells' + - clocks + +additionalProperties: false + +examples: + - | + serdes: serdes@10808000 { + compatible = "microchip,sparx5-serdes"; + #phy-cells = <1>; + clocks = <&sys_clk>; + reg = <0x10808000 0x5d0000>; + }; + +... -- 2.30.0