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From: Jianjun Wang <jianjun.wang@mediatek.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>, <maz@kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Ryder Lee <ryder.lee@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	<linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Sj Huang <sj.huang@mediatek.com>,
	Jianjun Wang <jianjun.wang@mediatek.com>,
	<youlin.pei@mediatek.com>, <chuanjia.liu@mediatek.com>,
	<qizhong.cheng@mediatek.com>, <sin_jieyang@mediatek.com>,
	<drinkcat@chromium.org>, <Rex-BC.Chen@mediatek.com>,
	<anson.chuang@mediatek.com>
Subject: [v8,0/7] PCI: mediatek: Add new generation controller support
Date: Wed, 24 Feb 2021 14:11:25 +0800	[thread overview]
Message-ID: <20210224061132.26526-1-jianjun.wang@mediatek.com> (raw)

These series patches add pcie-mediatek-gen3.c and dt-bindings file to
support new generation PCIe controller.

Changes in v8:
1. Add irq_clock to protect IRQ register access;
2. Mask all INTx interrupt when startup port;
3. Remove activate/deactivate callbacks from bottom_domain_ops;
4. Add unmask/mask callbacks in mtk_msi_bottom_irq_chip;
5. Add property information for reg-names.

Changes in v7:
1. Split the driver patch to core PCIe, INTx, MSI and PM patches;
2. Reshape MSI init and handle flow, use msi_bottom_domain to cover all sets;
3. Replace readl/writel with their relaxed version;
4. Add MSI description in binding document;
5. Add pl_250m clock in binding document.

Changes in v6:
1. Export pci_pio_to_address() to support compiling as kernel module;
2. Replace usleep_range(100 * 1000, 120 * 1000) with msleep(100);
3. Replace dev_notice with dev_err;
4. Fix MSI get hwirq flow;
5. Fix warning for possible recursive locking in mtk_pcie_set_affinity.

Changes in v5:
1. Remove unused macros
2. Modify the config read/write callbacks, set the config byte field
   in TLP header and use pci_generic_config_read32/write32
   to access the config space
3. Fix the settings of translation window, both MEM and IO regions
   works properly
4. Fix typos

Changes in v4:
1. Fix PCIe power up/down flow
2. Use "mac" and "phy" for reset names
3. Add clock names
4. Fix the variables type

Changes in v3:
1. Remove standard property in binding document
2. Return error number when get_optional* API throws an error
3. Use the bulk clk APIs

Changes in v2:
1. Fix the typo of dt-bindings patch
2. Remove the unnecessary properties in binding document
3. dispos the irq mappings of msi top domain when irq teardown

Jianjun Wang (7):
  dt-bindings: PCI: mediatek-gen3: Add YAML schema
  PCI: Export pci_pio_to_address() for module use
  PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192
  PCI: mediatek-gen3: Add INTx support
  PCI: mediatek-gen3: Add MSI support
  PCI: mediatek-gen3: Add system PM support
  MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer

 .../bindings/pci/mediatek-pcie-gen3.yaml      | 181 ++++
 MAINTAINERS                                   |   1 +
 drivers/pci/controller/Kconfig                |  13 +
 drivers/pci/controller/Makefile               |   1 +
 drivers/pci/controller/pcie-mediatek-gen3.c   | 994 ++++++++++++++++++
 drivers/pci/pci.c                             |   1 +
 6 files changed, 1191 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
 create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c

-- 
2.25.1


             reply	other threads:[~2021-02-24  6:13 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-24  6:11 Jianjun Wang [this message]
2021-02-24  6:11 ` [v8,1/7] dt-bindings: PCI: mediatek-gen3: Add YAML schema Jianjun Wang
2021-03-06 20:09   ` Rob Herring
2021-02-24  6:11 ` [v8,2/7] PCI: Export pci_pio_to_address() for module use Jianjun Wang
2021-02-24  6:11 ` [v8,3/7] PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192 Jianjun Wang
2021-02-24 13:36   ` Krzysztof Wilczyński
2021-02-25  3:07     ` Jianjun Wang
2021-03-11 12:38   ` Pali Rohár
2021-03-13  7:43     ` Jianjun Wang
2021-03-18  0:02       ` Pali Rohár
2021-03-18  5:48         ` Jianjun Wang
2021-03-19 18:53           ` Pali Rohár
2021-03-23  1:31             ` Jianjun Wang
2021-03-23 14:51               ` Pali Rohár
2021-03-29 22:58           ` Pali Rohár
2021-02-24  6:11 ` [v8,4/7] PCI: mediatek-gen3: Add INTx support Jianjun Wang
2021-02-24 14:24   ` Krzysztof Wilczyński
2021-02-25  3:10     ` Jianjun Wang
2021-03-09 11:10   ` Marc Zyngier
2021-03-10  3:05     ` Jianjun Wang
2021-02-24  6:11 ` [v8,5/7] PCI: mediatek-gen3: Add MSI support Jianjun Wang
2021-02-24 14:31   ` Krzysztof Wilczyński
2021-02-25  3:09     ` Jianjun Wang
2021-03-09 11:23   ` Marc Zyngier
2021-03-10  6:48     ` Jianjun Wang
     [not found]       ` <87a6rbxs4w.wl-maz@kernel.org>
2021-03-11  9:47         ` Jianjun Wang
2021-03-11  0:05   ` Pali Rohár
2021-03-11  8:19     ` Marc Zyngier
2021-03-11  9:50       ` Jianjun Wang
2021-02-24  6:11 ` [v8,6/7] PCI: mediatek-gen3: Add system PM support Jianjun Wang
2021-02-24 14:10   ` Krzysztof Wilczyński
2021-02-25  3:34     ` Jianjun Wang
2021-02-25 22:00       ` Krzysztof Wilczyński
2021-02-26 10:06         ` Jianjun Wang
2021-02-24  6:11 ` [v8,7/7] MAINTAINERS: Add Jianjun Wang as MediaTek PCI co-maintainer Jianjun Wang

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