From: Julien Thierry <jthierry@redhat.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com,
broonie@kernel.org, ycote@redhat.com,
Julien Thierry <jthierry@redhat.com>
Subject: [RFC PATCH v2 7/8] arm64: insn: Add some opcodes to instruction decoder
Date: Wed, 3 Mar 2021 18:05:35 +0100 [thread overview]
Message-ID: <20210303170536.1838032-8-jthierry@redhat.com> (raw)
In-Reply-To: <20210303170536.1838032-1-jthierry@redhat.com>
Add decoding capability for some instructions that objtool will need
to decode.
Signed-off-by: Julien Thierry <jthierry@redhat.com>
---
arch/arm64/include/asm/insn.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 185f52ef0228..388aa22eacb1 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -296,6 +296,12 @@ __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
__AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
__AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
__AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
+__AARCH64_INSN_FUNCS(store_imm, 0x3FC00000, 0x39000000)
+__AARCH64_INSN_FUNCS(load_imm, 0x3FC00000, 0x39400000)
+__AARCH64_INSN_FUNCS(store_pre, 0x3FE00C00, 0x38000C00)
+__AARCH64_INSN_FUNCS(load_pre, 0x3FE00C00, 0x38400C00)
+__AARCH64_INSN_FUNCS(store_post, 0x3FE00C00, 0x38000400)
+__AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400)
__AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
__AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
__AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
@@ -304,6 +310,8 @@ __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
__AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
__AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
__AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
+__AARCH64_INSN_FUNCS(stp, 0x7FC00000, 0x29000000)
+__AARCH64_INSN_FUNCS(ldp, 0x7FC00000, 0x29400000)
__AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
__AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
__AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
@@ -336,6 +344,7 @@ __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
__AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
__AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
__AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
+__AARCH64_INSN_FUNCS(mov_reg, 0x7FE0FFE0, 0x2A0003E0)
__AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
__AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
__AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
--
2.25.4
next prev parent reply other threads:[~2021-03-03 19:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 17:05 [RFC PATCH v2 0/8] arm64: Prepare instruction decoder for objtool Julien Thierry
2021-03-03 17:05 ` [RFC PATCH v2 1/8] arm64: Move patching utilities out of instruction encoding/decoding Julien Thierry
2021-03-03 17:05 ` [RFC PATCH v2 2/8] arm64: Move aarch32 condition check functions Julien Thierry
2021-03-03 17:05 ` [RFC PATCH v2 3/8] arm64: insn: Reduce header dependencies of instruction decoder Julien Thierry
2021-03-03 17:05 ` [RFC PATCH v2 4/8] arm64: Move instruction encoder/decoder under lib/ Julien Thierry
2021-03-03 17:05 ` [RFC PATCH v2 5/8] arm64: insn: Add SVE instruction class Julien Thierry
2021-03-03 17:05 ` [RFC PATCH v2 6/8] arm64: insn: Add barrier encodings Julien Thierry
2021-03-03 17:05 ` Julien Thierry [this message]
2021-03-03 17:05 ` [RFC PATCH v2 8/8] arm64: insn: Add load/store decoding helpers Julien Thierry
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