From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9262C41519 for ; Wed, 10 Mar 2021 22:06:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 972D364FD8 for ; Wed, 10 Mar 2021 22:06:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234122AbhCJWGI (ORCPT ); Wed, 10 Mar 2021 17:06:08 -0500 Received: from mga04.intel.com ([192.55.52.120]:5154 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233240AbhCJWFw (ORCPT ); Wed, 10 Mar 2021 17:05:52 -0500 IronPort-SDR: avlu+sgM8xZZpuL80rR8qc9j+7onPdgOfP5jocdlTXQEeWhMEuexOBCRV+zDkLevtCQHmYOqXw YfiGriaYvxgw== X-IronPort-AV: E=McAfee;i="6000,8403,9919"; a="186193996" X-IronPort-AV: E=Sophos;i="5.81,238,1610438400"; d="scan'208";a="186193996" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2021 14:05:49 -0800 IronPort-SDR: F6uL6gHRCkotCKXyTnfnY7IZBKpPBKWR0DfwlYZEukM0g4Ap2lIWsVlAcAI0E5QpXtb6PdmjvL FME80cmHZpsA== X-IronPort-AV: E=Sophos;i="5.81,238,1610438400"; d="scan'208";a="410368528" Received: from yyu32-desk.sc.intel.com ([143.183.136.146]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2021 14:05:48 -0800 From: Yu-cheng Yu To: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang , Pengfei Xu , Haitao Huang Cc: Yu-cheng Yu , Jarkko Sakkinen Subject: [PATCH v22 8/8] x86/vdso: Add ENDBR64 to __vdso_sgx_enter_enclave Date: Wed, 10 Mar 2021 14:05:19 -0800 Message-Id: <20210310220519.16811-9-yu-cheng.yu@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210310220519.16811-1-yu-cheng.yu@intel.com> References: <20210310220519.16811-1-yu-cheng.yu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When CET is enabled, __vdso_sgx_enter_enclave() needs an endbr64 in the beginning of the function. Signed-off-by: Yu-cheng Yu Cc: Andy Lutomirski Cc: Dave Hansen Cc: Jarkko Sakkinen --- arch/x86/entry/vdso/vsgx.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/entry/vdso/vsgx.S b/arch/x86/entry/vdso/vsgx.S index 86a0e94f68df..a70d4d09f713 100644 --- a/arch/x86/entry/vdso/vsgx.S +++ b/arch/x86/entry/vdso/vsgx.S @@ -27,6 +27,9 @@ SYM_FUNC_START(__vdso_sgx_enter_enclave) /* Prolog */ .cfi_startproc +#ifdef CONFIG_X86_CET + endbr64 +#endif push %rbp .cfi_adjust_cfa_offset 8 .cfi_rel_offset %rbp, 0 -- 2.21.0