[PATCH 0/5] arm64: sunxi: Enable the sun4i timer

[PATCH 0/5] arm64: sunxi: Enable the sun4i timer

[Samuel Holland]

In preparation for adding CPU idle states, hook up the sun4i timer.
Having a non-c3stop clockevent source available is necessary for all
CPUs to simultaneously enter a local-timer-stop idle state.

Samuel Holland (5):
  dt-bindings: timer: Simplify conditional expressions
  dt-bindings: timer: Add compatibles for sun50i timers
  arm64: dts: allwinner: a64: Sort watchdog node
  arm64: dts: allwinner: Add sun4i MMIO timer nodes
  arm64: sunxi: Build the sun4i timer driver

 .../timer/allwinner,sun4i-a10-timer.yaml      | 42 +++++++++----------
 arch/arm64/Kconfig.platforms                  |  1 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++----
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  9 ++++
 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |  9 ++++
 5 files changed, 55 insertions(+), 31 deletions(-)

-- 
2.26.2

[PATCH 1/5] dt-bindings: timer: Simplify conditional expressions

[Samuel Holland]

The sun4i timer IP block has a variable number of interrupts based on
the compatible. Use enums to combine the two sections for the existing
3-interrupt variants, and to simplify adding new compatible strings.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 .../timer/allwinner,sun4i-a10-timer.yaml      | 25 ++++++-------------
 1 file changed, 7 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 1c7cf32e7ac2..3462598e609d 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -34,8 +34,8 @@ allOf:
   - if:
       properties:
         compatible:
-          items:
-            const: allwinner,sun4i-a10-timer
+          enum:
+            - allwinner,sun4i-a10-timer
 
     then:
       properties:
@@ -46,8 +46,8 @@ allOf:
   - if:
       properties:
         compatible:
-          items:
-            const: allwinner,sun8i-a23-timer
+          enum:
+            - allwinner,sun8i-a23-timer
 
     then:
       properties:
@@ -58,20 +58,9 @@ allOf:
   - if:
       properties:
         compatible:
-          items:
-            const: allwinner,sun8i-v3s-timer
-
-    then:
-      properties:
-        interrupts:
-          minItems: 3
-          maxItems: 3
-
-  - if:
-      properties:
-        compatible:
-          items:
-            const: allwinner,suniv-f1c100s-timer
+          enum:
+            - allwinner,sun8i-v3s-timer
+            - allwinner,suniv-f1c100s-timer
 
     then:
       properties:
-- 
2.26.2

[PATCH 2/5] dt-bindings: timer: Add compatibles for sun50i timers

[Samuel Holland]

The sun50i SoCs contain timer blocks which are useful as broadcast
clockevent sources. They each have 2 interrupts, matching the A23
variant, so add the new compatible strings with the A23 compatible
as a fallback.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 .../timer/allwinner,sun4i-a10-timer.yaml        | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 3462598e609d..53fd24bdc34e 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -12,11 +12,18 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - allwinner,sun4i-a10-timer
-      - allwinner,sun8i-a23-timer
-      - allwinner,sun8i-v3s-timer
-      - allwinner,suniv-f1c100s-timer
+    oneOf:
+      - enum:
+          - allwinner,sun4i-a10-timer
+          - allwinner,sun8i-a23-timer
+          - allwinner,sun8i-v3s-timer
+          - allwinner,suniv-f1c100s-timer
+      - items:
+          - enum:
+              - allwinner,sun50i-a64-timer
+              - allwinner,sun50i-h6-timer
+              - allwinner,sun50i-h616-timer
+          - const: allwinner,sun8i-a23-timer
 
   reg:
     maxItems: 1
-- 
2.26.2

[PATCH 3/5] arm64: dts: allwinner: a64: Sort watchdog node

[Samuel Holland]

Nodes should be sorted by unit address. Move the watchdog node to the
correct place, so it will be next to the timer node when that is added.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 206693423aa6..33df866f6ea9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -905,6 +905,14 @@ uart4_rts_cts_pins: uart4-rts-cts-pins {
 			};
 		};
 
+		wdt0: watchdog@1c20ca0 {
+			compatible = "allwinner,sun50i-a64-wdt",
+				     "allwinner,sun6i-a31-wdt";
+			reg = <0x01c20ca0 0x20>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		spdif: spdif@1c21000 {
 			#sound-dai-cells = <0>;
 			compatible = "allwinner,sun50i-a64-spdif",
@@ -1436,13 +1444,5 @@ r_rsb: rsb@1f03400 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
-
-		wdt0: watchdog@1c20ca0 {
-			compatible = "allwinner,sun50i-a64-wdt",
-				     "allwinner,sun6i-a31-wdt";
-			reg = <0x01c20ca0 0x20>;
-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc24M>;
-		};
 	};
 };
-- 
2.26.2

[PATCH 4/5] arm64: dts: allwinner: Add sun4i MMIO timer nodes

[Samuel Holland]

For a CPU to enter an idle state, there must be some timer which can
trigger an IRQ to wake it back up. The local ARM architectural timer is
not sufficient, because that timer stops when the CPU is powered down.
Some other CPU's ARM architectural timer can be used, but this prevents
that other CPU from entering an idle state. So to allow all CPUs to
enter an idle state at the same time, some MMIO timer must be available
that is not tied to any CPU.

The basic "sun4i" timer seems most appropriate for this purpose due to
its moderate rate, balancing precision and power consumption.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  | 9 +++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi   | 9 +++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++
 3 files changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 33df866f6ea9..64e8b4a372cc 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -905,6 +905,15 @@ uart4_rts_cts_pins: uart4-rts-cts-pins {
 			};
 		};
 
+		timer@1c20c00 {
+			compatible = "allwinner,sun50i-a64-timer",
+				     "allwinner,sun8i-a23-timer";
+			reg = <0x01c20c00 0xa0>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		wdt0: watchdog@1c20ca0 {
 			compatible = "allwinner,sun50i-a64-wdt",
 				     "allwinner,sun6i-a31-wdt";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 62334054c710..9ba3b30e11fa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -332,6 +332,15 @@ cpu_speed_grade: cpu-speed-grade@1c {
 			};
 		};
 
+		timer@3009000 {
+			compatible = "allwinner,sun50i-h6-timer",
+				     "allwinner,sun8i-a23-timer";
+			reg = <0x03009000 0xa0>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		watchdog: watchdog@30090a0 {
 			compatible = "allwinner,sun50i-h6-wdt",
 				     "allwinner,sun6i-a31-wdt";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index c277b53f94ea..ff55712ce96e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -128,6 +128,15 @@ ccu: clock@3001000 {
 			#reset-cells = <1>;
 		};
 
+		timer@3009000 {
+			compatible = "allwinner,sun50i-h616-timer",
+				     "allwinner,sun8i-a23-timer";
+			reg = <0x03009000 0xa0>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
 		watchdog: watchdog@30090a0 {
 			compatible = "allwinner,sun50i-h616-wdt",
 				     "allwinner,sun6i-a31-wdt";
-- 
2.26.2

[PATCH 5/5] arm64: sunxi: Build the sun4i timer driver

[Samuel Holland]

While the ARM architectural timer is generatlly the best timer to use,
a non-c3stop timer is needed for cpuidle. Use the sun4i timer for this
purpose, which is present on all 64-bit sunxi SoCs.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/arm64/Kconfig.platforms | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index cdfd5fed457f..7f6a66431fa7 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -26,6 +26,7 @@ config ARCH_SUNXI
 	select IRQ_FASTEOI_HIERARCHY_HANDLERS
 	select PINCTRL
 	select RESET_CONTROLLER
+	select SUN4I_TIMER
 	help
 	  This enables support for Allwinner sunxi based SoCs like the A64.
 
-- 
2.26.2

Re: [PATCH 1/5] dt-bindings: timer: Simplify conditional expressions

[Maxime Ripard]

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On Sun, Mar 14, 2021 at 11:32:46PM -0500, Samuel Holland wrote:
> The sun4i timer IP block has a variable number of interrupts based on
> the compatible. Use enums to combine the two sections for the existing
> 3-interrupt variants, and to simplify adding new compatible strings.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Acked-by: Maxime Ripard <maxime@cerno.tech>

Thanks!
Maxime

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Re: [PATCH 2/5] dt-bindings: timer: Add compatibles for sun50i timers

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 417 bytes --]

On Sun, Mar 14, 2021 at 11:32:47PM -0500, Samuel Holland wrote:
> The sun50i SoCs contain timer blocks which are useful as broadcast
> clockevent sources. They each have 2 interrupts, matching the A23
> variant, so add the new compatible strings with the A23 compatible
> as a fallback.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Acked-by: Maxime Ripard <maxime@cerno.tech>

Thanks!
Maxime

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Re: [PATCH 4/5] arm64: dts: allwinner: Add sun4i MMIO timer nodes

[Jernej Škrabec]

Hi!

Dne ponedeljek, 15. marec 2021 ob 05:32:49 CET je Samuel Holland napisal(a):
> For a CPU to enter an idle state, there must be some timer which can
> trigger an IRQ to wake it back up. The local ARM architectural timer is
> not sufficient, because that timer stops when the CPU is powered down.
> Some other CPU's ARM architectural timer can be used, but this prevents
> that other CPU from entering an idle state. So to allow all CPUs to
> enter an idle state at the same time, some MMIO timer must be available
> that is not tied to any CPU.
> 
> The basic "sun4i" timer seems most appropriate for this purpose due to
> its moderate rate, balancing precision and power consumption.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  | 9 +++++++++
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi   | 9 +++++++++
>  arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++
>  3 files changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index
> 33df866f6ea9..64e8b4a372cc 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -905,6 +905,15 @@ uart4_rts_cts_pins: uart4-rts-cts-pins {
>  			};
>  		};
> 
> +		timer@1c20c00 {
> +			compatible = "allwinner,sun50i-a64-timer",
> +				     "allwinner,sun8i-a23-timer";
> +			reg = <0x01c20c00 0xa0>;
> +			interrupts = <GIC_SPI 18 
IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 19 
IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc24M>;
> +		};
> +
>  		wdt0: watchdog@1c20ca0 {
>  			compatible = "allwinner,sun50i-a64-wdt",
>  				     "allwinner,sun6i-a31-wdt";
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index
> 62334054c710..9ba3b30e11fa 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -332,6 +332,15 @@ cpu_speed_grade: cpu-speed-grade@1c {
>  			};
>  		};
> 
> +		timer@3009000 {
> +			compatible = "allwinner,sun50i-h6-timer",
> +				     "allwinner,sun8i-a23-timer";
> +			reg = <0x03009000 0xa0>;
> +			interrupts = <GIC_SPI 48 
IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 49 
IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc24M>;
> +		};
> +
>  		watchdog: watchdog@30090a0 {
>  			compatible = "allwinner,sun50i-h6-wdt",
>  				     "allwinner,sun6i-a31-wdt";
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index
> c277b53f94ea..ff55712ce96e 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi

This file does not exist yet upstream.

Best regards,
Jernej

> @@ -128,6 +128,15 @@ ccu: clock@3001000 {
>  			#reset-cells = <1>;
>  		};
> 
> +		timer@3009000 {
> +			compatible = "allwinner,sun50i-h616-timer",
> +				     "allwinner,sun8i-a23-timer";
> +			reg = <0x03009000 0xa0>;
> +			interrupts = <GIC_SPI 48 
IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 49 
IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&osc24M>;
> +		};
> +
>  		watchdog: watchdog@30090a0 {
>  			compatible = "allwinner,sun50i-h616-wdt",
>  				     "allwinner,sun6i-a31-wdt";

Re: [PATCH 4/5] arm64: dts: allwinner: Add sun4i MMIO timer nodes

[Samuel Holland]

On 3/15/21 1:32 PM, Jernej Škrabec wrote:
> Hi!
> 
> Dne ponedeljek, 15. marec 2021 ob 05:32:49 CET je Samuel Holland napisal(a):
>> For a CPU to enter an idle state, there must be some timer which can
>> trigger an IRQ to wake it back up. The local ARM architectural timer is
>> not sufficient, because that timer stops when the CPU is powered down.
>> Some other CPU's ARM architectural timer can be used, but this prevents
>> that other CPU from entering an idle state. So to allow all CPUs to
>> enter an idle state at the same time, some MMIO timer must be available
>> that is not tied to any CPU.
>>
>> The basic "sun4i" timer seems most appropriate for this purpose due to
>> its moderate rate, balancing precision and power consumption.
>>
>> Signed-off-by: Samuel Holland <samuel@sholland.org>
>> ---
>>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  | 9 +++++++++
>>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi   | 9 +++++++++
>>  arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++
>>  3 files changed, 27 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index
>> 33df866f6ea9..64e8b4a372cc 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> @@ -905,6 +905,15 @@ uart4_rts_cts_pins: uart4-rts-cts-pins {
>>  			};
>>  		};
>>
>> +		timer@1c20c00 {
>> +			compatible = "allwinner,sun50i-a64-timer",
>> +				     "allwinner,sun8i-a23-timer";
>> +			reg = <0x01c20c00 0xa0>;
>> +			interrupts = <GIC_SPI 18 
> IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 19 
> IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&osc24M>;
>> +		};
>> +
>>  		wdt0: watchdog@1c20ca0 {
>>  			compatible = "allwinner,sun50i-a64-wdt",
>>  				     "allwinner,sun6i-a31-wdt";
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index
>> 62334054c710..9ba3b30e11fa 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> @@ -332,6 +332,15 @@ cpu_speed_grade: cpu-speed-grade@1c {
>>  			};
>>  		};
>>
>> +		timer@3009000 {
>> +			compatible = "allwinner,sun50i-h6-timer",
>> +				     "allwinner,sun8i-a23-timer";
>> +			reg = <0x03009000 0xa0>;
>> +			interrupts = <GIC_SPI 48 
> IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 49 
> IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&osc24M>;
>> +		};
>> +
>>  		watchdog: watchdog@30090a0 {
>>  			compatible = "allwinner,sun50i-h6-wdt",
>>  				     "allwinner,sun6i-a31-wdt";
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index
>> c277b53f94ea..ff55712ce96e 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> 
> This file does not exist yet upstream.

Right. I will remove this section for v2.

Cheers,
Samuel

> Best regards,
> Jernej
> 
>> @@ -128,6 +128,15 @@ ccu: clock@3001000 {
>>  			#reset-cells = <1>;
>>  		};
>>
>> +		timer@3009000 {
>> +			compatible = "allwinner,sun50i-h616-timer",
>> +				     "allwinner,sun8i-a23-timer";
>> +			reg = <0x03009000 0xa0>;
>> +			interrupts = <GIC_SPI 48 
> IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 49 
> IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&osc24M>;
>> +		};
>> +
>>  		watchdog: watchdog@30090a0 {
>>  			compatible = "allwinner,sun50i-h616-wdt",
>>  				     "allwinner,sun6i-a31-wdt";
> 
> 
> 
>