From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C195C433E1 for ; Sun, 21 Mar 2021 20:47:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0BE9661955 for ; Sun, 21 Mar 2021 20:47:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbhCUUmq (ORCPT ); Sun, 21 Mar 2021 16:42:46 -0400 Received: from st43p00im-zteg10073401.me.com ([17.58.63.181]:36101 "EHLO st43p00im-zteg10073401.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230345AbhCUUmD (ORCPT ); Sun, 21 Mar 2021 16:42:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1616359320; bh=Ge/uIA5hLdNP9ltZO4wkWhRW01e4mo9aC5X6GiyNNoM=; h=From:To:Subject:Date:Message-Id; b=zmBo6PB35QK+CyVRfzChnBi2Ltf3M0+FnEjcZXq5KtSg6LVSV01UdN+ONwGoLKeaU LlHyh9K9Z+WVTtE7LBdH5IE7NhPMbgrUvwZn7dwyYhKfVCCAHUlBtjUI1jCSfHNSaK 8sYJ8owP0CZNCMuEUqAG3UQIWXaa4wnR2IABqr3DE3L3L59MR8bi+0UOeug0ZR9v+N 9Y7PeFN4TEdkCH2KbBfCfGBmeXercZjgNNogmE6WM3y8qphR+DsNIJktYM163vWxGP rJ9VwsEorX/4ezdOSdZHSndpV+nVoCr1UC9d5/lTsTOzKpZla9btKiMoGVkOffAqRF yqBfgvLh1iCAw== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-zteg10073401.me.com (Postfix) with ESMTPSA id 173D95E0181; Sun, 21 Mar 2021 20:41:59 +0000 (UTC) From: Alain Volmat To: Michael Turquette , Stephen Boyd , Rob Herring , Patrice Chotard Cc: Lee Jones , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alain Volmat Subject: [PATCH 11/16] ARM: dts: sti: update clkgen-pll entries in stih407-clock Date: Sun, 21 Mar 2021 21:40:33 +0100 Message-Id: <20210321204038.14417-12-avolmat@me.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210321204038.14417-1-avolmat@me.com> References: <20210321204038.14417-1-avolmat@me.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.761 definitions=2021-03-21_05:2021-03-19,2021-03-21 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=977 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-2006250000 definitions=main-2103210166 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The clkgen-pll driver now embed the clock names (assuming the right compatible is used). Remove all clock-output-names property and update when necessary the compatible. Signed-off-by: Alain Volmat --- arch/arm/boot/dts/stih407-clock.dtsi | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index ecd568777e5f..2603226a6ca8 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -36,8 +36,6 @@ compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; }; }; @@ -74,12 +72,9 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,clkgen-pll0"; + compatible = "st,clkgen-pll0-a0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; - clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,21 +107,16 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,clkgen-pll0"; + compatible = "st,clkgen-pll0-c0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; - clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,clkgen-pll1"; + compatible = "st,clkgen-pll1-c0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; }; clk_s_c0_flexgen: clk-s-c0-flexgen { -- 2.17.1