From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF16EC433DB for ; Mon, 29 Mar 2021 16:06:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B8F8F61987 for ; Mon, 29 Mar 2021 16:06:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230421AbhC2QGV (ORCPT ); Mon, 29 Mar 2021 12:06:21 -0400 Received: from foss.arm.com ([217.140.110.172]:56316 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230248AbhC2QGP (ORCPT ); Mon, 29 Mar 2021 12:06:15 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C7E02142F; Mon, 29 Mar 2021 09:06:14 -0700 (PDT) Received: from lpieralisi (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0B7333F719; Mon, 29 Mar 2021 09:06:12 -0700 (PDT) Date: Mon, 29 Mar 2021 17:06:07 +0100 From: Lorenzo Pieralisi To: Jim Quinlan Cc: Bjorn Helgaas , linux-pci@vger.kernel.org, Nicolas Saenz Julienne , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com, Rob Herring , Bjorn Helgaas , Florian Fainelli , Philipp Zabel , Jim Quinlan , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list Subject: Re: [PATCH v5 2/2] PCI: brcmstb: Use reset/rearm instead of deassert/assert Message-ID: <20210329160607.GA9677@lpieralisi> References: <20210312204556.5387-1-jim2101024@gmail.com> <20210312204556.5387-3-jim2101024@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210312204556.5387-3-jim2101024@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 12, 2021 at 03:45:55PM -0500, Jim Quinlan wrote: > The Broadcom STB PCIe RC uses a reset control "rescal" for certain chips. > The "rescal" implements a "pulse reset" so using assert/deassert is wrong > for this device. Instead, we use reset/rearm. We need to use rearm so > that we can reset it after a suspend/resume cycle; w/o using "rearm", the > "rescal" device will only ever fire once. > > Of course for suspend/resume to work we also need to put the reset/rearm > calls in the suspend and resume routines. > > Fixes: 740d6c3708a9 ("PCI: brcmstb: Add control of rescal reset") > Signed-off-by: Jim Quinlan > Acked-by: Florian Fainelli > --- > drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++------ > 1 file changed, 13 insertions(+), 6 deletions(-) Should I take this patch in the PCI queue ? Thanks, Lorenzo > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index e330e6811f0b..3b35d629035e 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -1148,6 +1148,7 @@ static int brcm_pcie_suspend(struct device *dev) > > brcm_pcie_turn_off(pcie); > ret = brcm_phy_stop(pcie); > + reset_control_rearm(pcie->rescal); > clk_disable_unprepare(pcie->clk); > > return ret; > @@ -1163,9 +1164,13 @@ static int brcm_pcie_resume(struct device *dev) > base = pcie->base; > clk_prepare_enable(pcie->clk); > > + ret = reset_control_reset(pcie->rescal); > + if (ret) > + goto err_disable_clk; > + > ret = brcm_phy_start(pcie); > if (ret) > - goto err; > + goto err_reset; > > /* Take bridge out of reset so we can access the SERDES reg */ > pcie->bridge_sw_init_set(pcie, 0); > @@ -1180,14 +1185,16 @@ static int brcm_pcie_resume(struct device *dev) > > ret = brcm_pcie_setup(pcie); > if (ret) > - goto err; > + goto err_reset; > > if (pcie->msi) > brcm_msi_set_regs(pcie->msi); > > return 0; > > -err: > +err_reset: > + reset_control_rearm(pcie->rescal); > +err_disable_clk: > clk_disable_unprepare(pcie->clk); > return ret; > } > @@ -1197,7 +1204,7 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) > brcm_msi_remove(pcie); > brcm_pcie_turn_off(pcie); > brcm_phy_stop(pcie); > - reset_control_assert(pcie->rescal); > + reset_control_rearm(pcie->rescal); > clk_disable_unprepare(pcie->clk); > } > > @@ -1278,13 +1285,13 @@ static int brcm_pcie_probe(struct platform_device *pdev) > return PTR_ERR(pcie->perst_reset); > } > > - ret = reset_control_deassert(pcie->rescal); > + ret = reset_control_reset(pcie->rescal); > if (ret) > dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); > > ret = brcm_phy_start(pcie); > if (ret) { > - reset_control_assert(pcie->rescal); > + reset_control_rearm(pcie->rescal); > clk_disable_unprepare(pcie->clk); > return ret; > } > -- > 2.17.1 >