From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BD4FC433E3 for ; Tue, 30 Mar 2021 17:50:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 279A5619D2 for ; Tue, 30 Mar 2021 17:50:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232591AbhC3RuH (ORCPT ); Tue, 30 Mar 2021 13:50:07 -0400 Received: from mga03.intel.com ([134.134.136.65]:47553 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232577AbhC3Rtf (ORCPT ); Tue, 30 Mar 2021 13:49:35 -0400 IronPort-SDR: kBaf9suBOUPVGcdpslmifk0FSCQlG4gVDFUYb9dKAtPrL14zqxdMJY22lC/+9PUd8P+z9fGJ2S m1OcMmOoZHWQ== X-IronPort-AV: E=McAfee;i="6000,8403,9939"; a="191851590" X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="scan'208";a="191851590" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 10:49:30 -0700 IronPort-SDR: FKvLAxU7/mf8+wi6h4BaZT9P8YOdspJgTsnJqqPxQyxc4VzrRXVhYEv6CxKxIvTfM2cRClkXwf b6SYPfDpn1+g== X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="scan'208";a="393695340" Received: from jacob-builder.jf.intel.com (HELO jacob-builder) ([10.7.199.155]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 10:49:30 -0700 Date: Tue, 30 Mar 2021 10:52:00 -0700 From: Jacob Pan To: Guenter Roeck Cc: LKML , iommu@lists.linux-foundation.org, Joerg Roedel , Lu Baolu , David Woodhouse , "Tian, Kevin" , Raj Ashok , Sanjay Kumar , Jean-Philippe Brucker , jacob.jun.pan@linux.intel.com, "Luck, Tony" Subject: Re: [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM Message-ID: <20210330105200.418bc42b@jacob-builder> In-Reply-To: <20210322175338.GA24424@roeck-us.net> References: <1614680040-1989-1-git-send-email-jacob.jun.pan@linux.intel.com> <1614680040-1989-2-git-send-email-jacob.jun.pan@linux.intel.com> <20210322175338.GA24424@roeck-us.net> Organization: OTC X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Guenter, On Mon, 22 Mar 2021 10:53:38 -0700, Guenter Roeck wrote: > On Tue, Mar 02, 2021 at 02:13:57AM -0800, Jacob Pan wrote: > > Write protect bit, when set, inhibits supervisor writes to the read-only > > pages. In supervisor shared virtual addressing (SVA), where page tables > > are shared between CPU and DMA, IOMMU PASID entry WPE bit should match > > CR0.WP bit in the CPU. > > This patch sets WPE bit for supervisor PASIDs if CR0.WP is set. > > > > Signed-off-by: Sanjay Kumar > > Signed-off-by: Jacob Pan > > --- > > ia64:defconfig: > > drivers/iommu/intel/pasid.c: In function 'pasid_enable_wpe': > drivers/iommu/intel/pasid.c:536:22: error: implicit declaration of > function 'read_cr0' drivers/iommu/intel/pasid.c:539:23: error: > 'X86_CR0_WP' undeclared > > Maybe it _is_ time to retire ia64 ? Good catch, sorry for the late reply. I guess otherwise I will have to do some #ifdef? There are many basic x86 helpers are missing in ia64. +Tony Thanks, Jacob