From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>,
<linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH 16/24] dt-bindings: atmel-sysreg: add bindings for sama7g5
Date: Wed, 31 Mar 2021 13:59:00 +0300 [thread overview]
Message-ID: <20210331105908.23027-17-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210331105908.23027-1-claudiu.beznea@microchip.com>
Add RAM controller and RAM PHY controller DT bindings.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
.../devicetree/bindings/arm/atmel-sysregs.txt | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 807264a78edc..7cd55a760d41 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
- "microchip,sam9x60-ddramc"
+ "microchip,sam9x60-ddramc",
+ "microchip,sama7g5-uddrc"
- reg: Should contain registers location and length
Examples:
@@ -55,6 +56,18 @@ Examples:
reg = <0xffffe800 0x200>;
};
+RAMC PHY Controller required properties:
+- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
+- reg: Should contain registers location and length
+
+Example:
+
+ ddr3phy: ddr3phy@e3804000 {
+ compatible = "microchip,sama7g5-ddr3phy", "syscon";
+ reg = <0xe3804000 0x1000>;
+ status = "okay";
+};
+
SHDWC Shutdown Controller
required properties:
--
2.25.1
next prev parent reply other threads:[~2021-03-31 11:01 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 10:58 [PATCH 00/24] ARM: at91: pm: add support for sama7g5 Claudiu Beznea
2021-03-31 10:58 ` [PATCH 01/24] ARM: at91: pm: move pm_bu to soc_pm data structure Claudiu Beznea
2021-03-31 14:44 ` Alexandre Belloni
2021-03-31 10:58 ` [PATCH 02/24] ARM: at91: pm: move the setup of soc_pm.bu->suspended Claudiu Beznea
2021-03-31 10:58 ` [PATCH 03/24] ARM: at91: pm: document at91_soc_pm structure Claudiu Beznea
2021-03-31 10:58 ` [PATCH 04/24] ARM: at91: pm: check for different controllers in at91_pm_modes_init() Claudiu Beznea
2021-03-31 10:58 ` [PATCH 05/24] ARM: at91: pm: do not initialize pdev Claudiu Beznea
2021-03-31 10:58 ` [PATCH 06/24] ARM: at91: pm: use r7 instead of tmp1 Claudiu Beznea
2021-03-31 10:58 ` [PATCH 07/24] ARM: at91: pm: avoid push and pop on stack while memory is in self-refersh Claudiu Beznea
2021-03-31 10:58 ` [PATCH 08/24] ARM: at91: pm: s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g Claudiu Beznea
2021-03-31 10:58 ` [PATCH 09/24] ARM: at91: pm: add support for waiting MCK1..4 Claudiu Beznea
2021-03-31 10:58 ` [PATCH 10/24] ARM: at91: sfrbu: add sfrbu registers definitions for sama7g5 Claudiu Beznea
2021-03-31 15:54 ` Alexandre Belloni
2021-04-01 9:34 ` Claudiu.Beznea
2021-03-31 10:58 ` [PATCH 11/24] ARM: at91: ddr: add registers definitions for sama7g5's ddr Claudiu Beznea
2021-03-31 10:58 ` [PATCH 12/24] ARM: at91: pm: add self-refresh support for sama7g5 Claudiu Beznea
2021-03-31 10:58 ` [PATCH 13/24] ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes Claudiu Beznea
2021-03-31 10:58 ` [PATCH 14/24] ARM: at91: pm: add support for 2.5V LDO regulator control Claudiu Beznea
2021-03-31 10:58 ` [PATCH 15/24] ARM: at91: pm: wait for ddr power mode off Claudiu Beznea
2021-03-31 10:59 ` Claudiu Beznea [this message]
2021-03-31 10:59 ` [PATCH 17/24] ARM: at91: pm: add sama7g5 ddr controller Claudiu Beznea
2021-03-31 10:59 ` [PATCH 18/24] ARM: at91: pm: add sama7g5 ddr phy controller Claudiu Beznea
2021-03-31 10:59 ` [PATCH 19/24] ARM: at91: pm: save ddr phy calibration data to securam Claudiu Beznea
2021-03-31 10:59 ` [PATCH 20/24] ARM: at91: pm: add backup mode support for SAMA7G5 Claudiu Beznea
2021-03-31 10:59 ` [PATCH 21/24] ARM: at91: pm: add sama7g5's pmc Claudiu Beznea
2021-03-31 10:59 ` [PATCH 22/24] ARM: at91: sama7: introduce sama7 SoC family Claudiu Beznea
2021-03-31 16:01 ` Alexandre Belloni
2021-04-01 9:38 ` Claudiu.Beznea
2021-04-01 10:24 ` Claudiu.Beznea
2021-04-08 15:24 ` Nicolas Ferre
2021-04-08 17:44 ` Alexandre Belloni
2021-04-08 15:30 ` Nicolas Ferre
2021-03-31 10:59 ` [PATCH 23/24] ARM: at91: pm: add pm support for SAMA7G5 Claudiu Beznea
2021-03-31 10:59 ` [PATCH 24/24] ARM: at91: pm: add sama7g5 shdwc Claudiu Beznea
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210331105908.23027-17-claudiu.beznea@microchip.com \
--to=claudiu.beznea@microchip.com \
--cc=alexandre.belloni@bootlin.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=ludovic.desroches@microchip.com \
--cc=nicolas.ferre@microchip.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).