From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82948C4361A for ; Wed, 31 Mar 2021 20:44:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 608A16108E for ; Wed, 31 Mar 2021 20:44:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236733AbhCaUnl (ORCPT ); Wed, 31 Mar 2021 16:43:41 -0400 Received: from st43p00im-ztbu10073601.me.com ([17.58.63.184]:33671 "EHLO st43p00im-ztbu10073601.me.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236633AbhCaUn1 (ORCPT ); Wed, 31 Mar 2021 16:43:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1617223406; bh=Q2D+GfnSz9xlfYItrPsH8bhVvd92JdmC7OMWqbsn6Zw=; h=From:To:Subject:Date:Message-Id; b=vnotX8ZGjvIBk2RMX/1TikNR7IHcvwuXwl1hthdhpcHNIgDfJiP0H8O4gqo5Si+Tv S424VOgTrcsEmIOJFG+3a7dGpe9rBDDD9smOhEoaYCDuY8DzFRtUDxC00a8RzZ5bXM uazq9zZ9DmXXsjGTgtuktumqcA8M3yoZD4MdCbQxpCOz+Pi4GsEekxY1u75O+dp0Xe RllbRc//eJShfk0ffu+Qq3+ffrWS+aaEEhbuuQdmf7q/ZM0R5V3O5JZoHu/RPiJWER KWl8Q/IpH4cpyzRhBV17ShjgMhW/+TvKEHZDnKH3gKGHvjaAit8ib45EJcXRSOM2dG Rke9IuFv9wNmA== Received: from localhost (101.220.150.77.rev.sfr.net [77.150.220.101]) by st43p00im-ztbu10073601.me.com (Postfix) with ESMTPSA id 2860582085F; Wed, 31 Mar 2021 20:43:26 +0000 (UTC) From: Alain Volmat To: Patrice Chotard , Rob Herring Cc: Arnd Bergmann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avolmat@me.com Subject: [PATCH v3 06/13] ARM: dts: sti: update clkgen-pll entries in stih418-clock Date: Wed, 31 Mar 2021 22:42:21 +0200 Message-Id: <20210331204228.26107-7-avolmat@me.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210331204228.26107-1-avolmat@me.com> References: <20210331204228.26107-1-avolmat@me.com> X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.369,18.0.761,17.0.607.475.0000000_definitions?= =?UTF-8?Q?=3D2021-03-31=5F08:2021-03-30=5F02,2021-03-31=5F08,2020-04-07?= =?UTF-8?Q?=5F01_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 mlxscore=0 spamscore=0 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 phishscore=0 mlxlogscore=994 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103310144 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The clkgen-pll driver now embed the clock names (assuming the right compatible is used). Remove all clock-output-names property and update when necessary the compatible. Signed-off-by: Alain Volmat --- arch/arm/boot/dts/stih418-clock.dtsi | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index 35d12979cdf4..d628e656458d 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -39,8 +39,6 @@ compatible = "st,stih418-clkgen-plla9"; clocks = <&clk_sysin>; - - clock-output-names = "clockgen-a9-pll-odf"; }; }; @@ -75,11 +73,9 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,clkgen-pll0"; + compatible = "st,clkgen-pll0-a0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-a0-pll-ofd-0"; }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -111,20 +107,16 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,clkgen-pll0"; + compatible = "st,clkgen-pll0-c0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll0-odf-0"; }; clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,clkgen-pll1"; + compatible = "st,clkgen-pll1-c0"; clocks = <&clk_sysin>; - - clock-output-names = "clk-s-c0-pll1-odf-0"; }; clk_s_c0_flexgen: clk-s-c0-flexgen { -- 2.17.1