From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: maz@kernel.org, mathieu.poirier@linaro.org
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
mike.leach@linaro.org, catalin.marinas@arm.com, will@kernel.org,
peterz@infradead.org, leo.yan@linaro.org, robh@kernel.org,
Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v6 11/20] coresight: etm4x: Add support for PE OS lock
Date: Mon, 5 Apr 2021 17:42:58 +0100 [thread overview]
Message-ID: <20210405164307.1720226-12-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210405164307.1720226-1-suzuki.poulose@arm.com>
ETE may not implement the OS lock and instead could rely on
the PE OS Lock for the trace unit access. This is indicated
by the TRCOLSR.OSM == 0b100. Add support for handling the
PE OS lock
Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: mike.leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
.../coresight/coresight-etm4x-core.c | 50 +++++++++++++++----
drivers/hwtracing/coresight/coresight-etm4x.h | 15 ++++++
2 files changed, 56 insertions(+), 9 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 00297906669c..35802caca32a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -115,30 +115,59 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
}
}
-static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa)
+static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
+ struct csdev_access *csa)
{
- /* Writing 0 to TRCOSLAR unlocks the trace registers */
- etm4x_relaxed_write32(csa, 0x0, TRCOSLAR);
- drvdata->os_unlock = true;
+ u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
+
+ drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
+}
+
+static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
+ struct csdev_access *csa, u32 val)
+{
+ val = !!val;
+
+ switch (drvdata->os_lock_model) {
+ case ETM_OSLOCK_PRESENT:
+ etm4x_relaxed_write32(csa, val, TRCOSLAR);
+ break;
+ case ETM_OSLOCK_PE:
+ write_sysreg_s(val, SYS_OSLAR_EL1);
+ break;
+ default:
+ pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
+ smp_processor_id(), drvdata->os_lock_model);
+ fallthrough;
+ case ETM_OSLOCK_NI:
+ return;
+ }
isb();
}
+static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
+ struct csdev_access *csa)
+{
+ WARN_ON(drvdata->cpu != smp_processor_id());
+
+ /* Writing 0 to OS Lock unlocks the trace unit registers */
+ etm_write_os_lock(drvdata, csa, 0x0);
+ drvdata->os_unlock = true;
+}
+
static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
{
if (!WARN_ON(!drvdata->csdev))
etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
-
}
static void etm4_os_lock(struct etmv4_drvdata *drvdata)
{
if (WARN_ON(!drvdata->csdev))
return;
-
- /* Writing 0x1 to TRCOSLAR locks the trace registers */
- etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR);
+ /* Writing 0x1 to OS Lock locks the trace registers */
+ etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
drvdata->os_unlock = false;
- isb();
}
static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
@@ -937,6 +966,9 @@ static void etm4_init_arch_data(void *info)
if (!etm4_init_csdev_access(drvdata, csa))
return;
+ /* Detect the support for OS Lock before we actually use it */
+ etm_detect_os_lock(drvdata, csa);
+
/* Make sure all registers are accessible */
etm4_os_unlock_csa(drvdata, csa);
etm4_cs_unlock(drvdata, csa);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index f6478ef642bf..5b961c5b78d1 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -505,6 +505,20 @@
ETM_MODE_EXCL_KERN | \
ETM_MODE_EXCL_USER)
+/*
+ * TRCOSLSR.OSLM advertises the OS Lock model.
+ * OSLM[2:0] = TRCOSLSR[4:3,0]
+ *
+ * 0b000 - Trace OS Lock is not implemented.
+ * 0b010 - Trace OS Lock is implemented.
+ * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
+ */
+#define ETM_OSLOCK_NI 0b000
+#define ETM_OSLOCK_PRESENT 0b010
+#define ETM_OSLOCK_PE 0b100
+
+#define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
+
/*
* TRCDEVARCH Bit field definitions
* Bits[31:21] - ARCHITECT = Always Arm Ltd.
@@ -898,6 +912,7 @@ struct etmv4_drvdata {
u8 s_ex_level;
u8 ns_ex_level;
u8 q_support;
+ u8 os_lock_model;
bool sticky_enable;
bool boot_enable;
bool os_unlock;
--
2.24.1
next prev parent reply other threads:[~2021-04-05 16:43 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-05 16:42 [PATCH v6 00/20] coresight: Add support for ETE and TRBE Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 01/20] perf: aux: Add flags for the buffer format Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 02/20] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 03/20] arm64: Add support for trace synchronization barrier Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 04/20] arm64: Add TRBE definitions Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 05/20] kvm: arm64: Handle access to TRFCR_EL1 Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 06/20] kvm: arm64: Move SPE availability check to VCPU load Suzuki K Poulose
2021-04-08 15:14 ` Alexandru Elisei
2021-04-05 16:42 ` [PATCH v6 07/20] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 08/20] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 09/20] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose
2021-04-05 16:42 ` [PATCH v6 10/20] coresight: Do not scan for graph if none is present Suzuki K Poulose
2021-04-05 16:42 ` Suzuki K Poulose [this message]
2021-04-05 16:42 ` [PATCH v6 12/20] coresight: ete: Add support for ETE sysreg access Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 13/20] coresight: ete: Add support for ETE tracing Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 14/20] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 15/20] coresight: etm-perf: Handle stale output handles Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 16/20] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 17/20] coresight: sink: Add TRBE driver Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 18/20] Documentation: coresight: trbe: Sysfs ABI description Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 19/20] Documentation: trace: Add documentation for TRBE Suzuki K Poulose
2021-04-05 16:43 ` [PATCH v6 20/20] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose
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