From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED87EC433B4 for ; Fri, 9 Apr 2021 02:08:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C055961105 for ; Fri, 9 Apr 2021 02:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232683AbhDICIM (ORCPT ); Thu, 8 Apr 2021 22:08:12 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:34482 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232426AbhDICIL (ORCPT ); Thu, 8 Apr 2021 22:08:11 -0400 X-UUID: 6ccd716d3a164f73934b28d8b445ff5e-20210409 X-UUID: 6ccd716d3a164f73934b28d8b445ff5e-20210409 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2040765411; Fri, 09 Apr 2021 10:07:57 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 9 Apr 2021 10:07:50 +0800 Received: from localhost.localdomain (10.15.20.246) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 9 Apr 2021 10:07:44 +0800 From: Mason Zhang To: Rob Herring , Matthias Brugger CC: , , , , , , Mason Zhang Subject: [PATCH v2 1/1] arm64: dts: mediatek: add MT6779 spi master dts node Date: Fri, 9 Apr 2021 09:56:52 +0800 Message-ID: <20210409015651.11474-1-Mason.Zhang@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add address-cells && size-cells in spi node based on patch v1. Signed-off-by: Mason Zhang --- arch/arm64/boot/dts/mediatek/mt6779.dtsi | 112 +++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 370f309d32de..c81e76865d1b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -219,6 +219,118 @@ status = "disabled"; }; + spi0: spi0@1100a000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi1: spi1@11010000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi2: spi2@11012000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi3: spi3@11013000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi4: spi4@11018000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi5: spi5@11019000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi6: spi6@1101d000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x1101d000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI6>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi7: spi7@1101e000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x1101e000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI7>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + audio: clock-controller@11210000 { compatible = "mediatek,mt6779-audio", "syscon"; reg = <0 0x11210000 0 0x1000>; -- 2.18.0