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From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>,
	<linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v2 19/24] ARM: at91: pm: save ddr phy calibration data to securam
Date: Fri, 9 Apr 2021 14:13:40 +0300	[thread overview]
Message-ID: <20210409111345.294472-20-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210409111345.294472-1-claudiu.beznea@microchip.com>

The resuming from backup mode is done with the help of bootloader.
The bootloader reconfigure the DDR controller and DDR PHY controller.
To speed-up the resuming process save the PHY calibration data into
SECURAM before suspending (securam is powered on backup mode).
This data will be later used by bootloader in DDR PHY reconfiguration
process. Also, in the process or recalibration the first 8 words of
the memory may get corrupted. To solve this, these 8 words are saved
in the securam and restored by bootloader in the process of PHY
configuration.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/mach-at91/pm.c | 60 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 59 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4dec7216a80e..91b4014d2e10 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -10,6 +10,7 @@
 #include <linux/io.h>
 #include <linux/of_address.h>
 #include <linux/of.h>
+#include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 #include <linux/parser.h>
 #include <linux/suspend.h>
@@ -27,18 +28,23 @@
 #include "generic.h"
 #include "pm.h"
 
+#define BACKUP_DDR_PHY_CALIBRATION	(9)
+
 /**
  * struct at91_pm_bu - AT91 power management backup unit data structure
  * @suspended: true if suspended to backup mode
  * @reserved: reserved
  * @canary: canary data for memory checking after exit from backup mode
  * @resume: resume API
+ * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
+ * of the memory
  */
 struct at91_pm_bu {
 	int suspended;
 	unsigned long reserved;
 	phys_addr_t canary;
 	phys_addr_t resume;
+	unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
 };
 
 /**
@@ -48,6 +54,7 @@ struct at91_pm_bu {
  * @ws_ids: wakup sources of_device_id array
  * @data: PM data to be used on last phase of suspend
  * @bu: backup unit mapped data (for backup mode)
+ * @memcs: memory chip select
  */
 struct at91_soc_pm {
 	int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
@@ -55,6 +62,7 @@ struct at91_soc_pm {
 	const struct of_device_id *ws_ids;
 	struct at91_pm_bu *bu;
 	struct at91_pm_data data;
+	void *memcs;
 };
 
 /**
@@ -316,6 +324,19 @@ extern u32 at91_pm_suspend_in_sram_sz;
 
 static int at91_suspend_finish(unsigned long val)
 {
+	int i;
+
+	if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
+		/*
+		 * The 1st 8 words of memory might get corrupted in the process
+		 * of DDR PHY recalibration; it is saved here in securam and it
+		 * will be restored later, after recalibration, by bootloader
+		 */
+		for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
+			soc_pm.bu->ddr_phy_calibration[i] =
+				*((unsigned int *)soc_pm.memcs + (i - 1));
+	}
+
 	flush_cache_all();
 	outer_disable();
 
@@ -673,12 +694,40 @@ static bool __init at91_is_pm_mode_active(int pm_mode)
 		soc_pm.data.suspend_mode == pm_mode);
 }
 
+static int __init at91_pm_backup_scan_memcs(unsigned long node,
+					    const char *uname, int depth,
+					    void *data)
+{
+	const char *type;
+	const __be32 *reg;
+	int *located = data;
+	int size;
+
+	/* Memory node already located. */
+	if (*located)
+		return 0;
+
+	type = of_get_flat_dt_prop(node, "device_type", NULL);
+
+	/* We are scanning "memory" nodes only. */
+	if (!type || strcmp(type, "memory"))
+		return 0;
+
+	reg = of_get_flat_dt_prop(node, "reg", &size);
+	if (reg) {
+		soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
+		*located = 1;
+	}
+
+	return 0;
+}
+
 static int __init at91_pm_backup_init(void)
 {
 	struct gen_pool *sram_pool;
 	struct device_node *np;
 	struct platform_device *pdev;
-	int ret = -ENODEV;
+	int ret = -ENODEV, located = 0;
 
 	if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
 		return -EPERM;
@@ -713,6 +762,15 @@ static int __init at91_pm_backup_init(void)
 	soc_pm.bu->suspended = 0;
 	soc_pm.bu->canary = __pa_symbol(&canary);
 	soc_pm.bu->resume = __pa_symbol(cpu_resume);
+	if (soc_pm.data.ramc_phy) {
+		of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
+		if (!located)
+			goto securam_fail;
+
+		/* DDR3PHY_ZQ0SR0 */
+		soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
+							  0x188);
+	}
 
 	return 0;
 
-- 
2.25.1


  parent reply	other threads:[~2021-04-09 11:17 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09 11:13 [PATCH v2 00/24] ARM: at91: pm: add support for sama7g5 Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 01/24] ARM: at91: pm: move pm_bu to soc_pm data structure Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 02/24] ARM: at91: pm: move the setup of soc_pm.bu->suspended Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 03/24] ARM: at91: pm: document at91_soc_pm structure Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 04/24] ARM: at91: pm: check for different controllers in at91_pm_modes_init() Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 05/24] ARM: at91: pm: do not initialize pdev Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 06/24] ARM: at91: pm: use r7 instead of tmp1 Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 07/24] ARM: at91: pm: avoid push and pop on stack while memory is in self-refersh Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 08/24] ARM: at91: pm: s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 09/24] ARM: at91: pm: add support for waiting MCK1..4 Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 10/24] ARM: at91: sfrbu: add sfrbu registers definitions for sama7g5 Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 11/24] ARM: at91: ddr: add registers definitions for sama7g5's ddr Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 12/24] ARM: at91: pm: add self-refresh support for sama7g5 Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 13/24] ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 14/24] ARM: at91: pm: add support for 2.5V LDO regulator control Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 15/24] ARM: at91: pm: wait for ddr power mode off Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 16/24] dt-bindings: atmel-sysreg: add bindings for sama7g5 Claudiu Beznea
2021-04-12 16:02   ` Rob Herring
2021-04-15  7:31     ` Claudiu.Beznea
2021-04-09 11:13 ` [PATCH v2 17/24] ARM: at91: pm: add sama7g5 ddr controller Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 18/24] ARM: at91: pm: add sama7g5 ddr phy controller Claudiu Beznea
2021-04-09 11:13 ` Claudiu Beznea [this message]
2021-04-09 11:13 ` [PATCH v2 20/24] ARM: at91: pm: add backup mode support for SAMA7G5 Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 21/24] ARM: at91: pm: add sama7g5's pmc Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 22/24] ARM: at91: sama7: introduce sama7 SoC family Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 23/24] ARM: at91: pm: add pm support for SAMA7G5 Claudiu Beznea
2021-04-09 11:13 ` [PATCH v2 24/24] ARM: at91: pm: add sama7g5 shdwc Claudiu Beznea

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