From: Rob Herring <robh@kernel.org>
To: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Cc: davem@davemloft.net, kuba@kernel.org, michal.simek@xilinx.com,
vkoul@kernel.org, devicetree@vger.kernel.org,
netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@xilinx.com
Subject: Re: [RFC PATCH 2/3] dt-bindings: net: xilinx_axienet: Introduce dmaengine binding support
Date: Mon, 12 Apr 2021 13:30:28 -0500 [thread overview]
Message-ID: <20210412183028.GA4156095@robh.at.kernel.org> (raw)
In-Reply-To: <1617992002-38028-3-git-send-email-radhey.shyam.pandey@xilinx.com>
On Fri, Apr 09, 2021 at 11:43:21PM +0530, Radhey Shyam Pandey wrote:
> The axiethernet driver will now use dmaengine framework to communicate
> with dma controller IP instead of built-in dma programming sequence.
>
> To request dma transmit and receive channels the axiethernet driver uses
> generic dmas, dma-names properties. It deprecates axistream-connected
Huh, you just added the property and now deprecating?
> property, remove axidma reg and interrupt properties from the ethernet
> node. Just to highlight that these DT changes are not backward compatible
> due to major driver restructuring/cleanup done in adopting the dmaengine
> framework.
Aren't users going to care this isn't a backwards compatible change?
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
> ---
> .../devicetree/bindings/net/xilinx_axienet.yaml | 40 +++++++++++++---------
> 1 file changed, 24 insertions(+), 16 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.yaml b/Documentation/devicetree/bindings/net/xilinx_axienet.yaml
> index 6a00e03e8804..0ea3972fefef 100644
> --- a/Documentation/devicetree/bindings/net/xilinx_axienet.yaml
> +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.yaml
> @@ -14,10 +14,8 @@ description: |
> offloading TX/RX checksum calculation off the processor.
>
> Management configuration is done through the AXI interface, while payload is
> - sent and received through means of an AXI DMA controller. This driver
> - includes the DMA driver code, so this driver is incompatible with AXI DMA
> - driver.
> -
> + sent and received through means of an AXI DMA controller using dmaengine
> + framework.
>
> allOf:
> - $ref: "ethernet-controller.yaml#"
> @@ -36,19 +34,13 @@ properties:
>
> reg:
> description:
> - Address and length of the IO space, as well as the address
> - and length of the AXI DMA controller IO space, unless
> - axistream-connected is specified, in which case the reg
> - attribute of the node referenced by it is used.
> - maxItems: 2
> + Address and length of the IO space.
> + maxItems: 1
>
> interrupts:
> description:
> - Can point to at most 3 interrupts. TX DMA, RX DMA, and optionally Ethernet
> - core. If axistream-connected is specified, the TX/RX DMA interrupts should
> - be on that node instead, and only the Ethernet core interrupt is optionally
> - specified here.
> - maxItems: 3
> + Ethernet core interrupt.
> + maxItems: 1
>
> phy-handle: true
>
> @@ -109,15 +101,29 @@ properties:
> for the AXI DMA controller used by this device. If this is specified,
> the DMA-related resources from that device (DMA registers and DMA
> TX/RX interrupts) rather than this one will be used.
> + deprecated: true
>
> mdio: true
>
> + dmas:
> + items:
> + - description: TX DMA Channel phandle and DMA request line number
> + - description: RX DMA Channel phandle and DMA request line number
> +
> + dma-names:
> + items:
> + - const: tx_chan0
> + - const: rx_chan0
> +
> +
> required:
> - compatible
> - reg
> - interrupts
> - xlnx,rxmem
> - phy-handle
> + - dmas
> + - dma-names
>
> additionalProperties: false
>
> @@ -127,11 +133,13 @@ examples:
> compatible = "xlnx,axi-ethernet-1.00.a";
> device_type = "network";
> interrupt-parent = <µblaze_0_axi_intc>;
> - interrupts = <2>, <0>, <1>;
> + interrupts = <1>;
> clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
> clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
> phy-mode = "mii";
> - reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>;
> + reg = <0x40c00000 0x40000>;
> + dmas = <&xilinx_dma 0>, <&xilinx_dma 1>;
> + dma-names = "tx_chan0", "rx_chan0";
Is there a chan1? Typical dma-names are just 'tx' and 'rx'.
> xlnx,rxcsum = <0x2>;
> xlnx,rxmem = <0x800>;
> xlnx,txcsum = <0x2>;
> --
> 2.7.4
>
next prev parent reply other threads:[~2021-04-12 18:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 18:13 [RFC PATCH 0/3] net: axienet: Introduce dmaengine support Radhey Shyam Pandey
2021-04-09 18:13 ` [RFC PATCH 1/3] dt-bindings: net: xilinx_axienet: convert bindings document to yaml Radhey Shyam Pandey
2021-04-12 13:20 ` Rob Herring
2021-04-09 18:13 ` [RFC PATCH 2/3] dt-bindings: net: xilinx_axienet: Introduce dmaengine binding support Radhey Shyam Pandey
2021-04-12 18:30 ` Rob Herring [this message]
2021-06-11 13:12 ` Radhey Shyam Pandey
2021-04-09 18:13 ` [RFC PATCH 3/3] net: axienet: Introduce dmaengine support Radhey Shyam Pandey
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