From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52A40C433ED for ; Wed, 14 Apr 2021 11:26:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EDF4613C3 for ; Wed, 14 Apr 2021 11:26:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350515AbhDNL0c (ORCPT ); Wed, 14 Apr 2021 07:26:32 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:16461 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234042AbhDNLZl (ORCPT ); Wed, 14 Apr 2021 07:25:41 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FL0T259cvztWGR; Wed, 14 Apr 2021 19:23:02 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.82.32) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Wed, 14 Apr 2021 19:25:08 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , Subject: [PATCH v4 11/16] arm64/mm: Introduce a callback to flush the local context Date: Wed, 14 Apr 2021 12:23:07 +0100 Message-ID: <20210414112312.13704-12-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210414112312.13704-1-shameerali.kolothum.thodi@huawei.com> References: <20210414112312.13704-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.47.82.32] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Julien Grall Flushing the local context will vary depending on the actual user of the ASID allocator. Introduce a new callback to flush the local context and move the call to flush local TLB in it. Signed-off-by: Julien Grall Signed-off-by: Shameer Kolothum --- arch/arm64/mm/context.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 901472a57b5d..ee446f7535a3 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -32,6 +32,8 @@ static struct asid_info unsigned long *pinned_map; unsigned long max_pinned_asids; unsigned long nr_pinned_asids; + /* Callback to locally flush the context. */ + void (*flush_cpu_ctxt_cb)(void); } asid_info; #define active_asid(info, cpu) (*per_cpu_ptr((info)->active, cpu)) @@ -245,8 +247,9 @@ static void asid_new_context(struct asid_info *info, atomic64_t *pasid, atomic64_set(pasid, asid); } - if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending)) - local_flush_tlb_all(); + if (cpumask_test_and_clear_cpu(cpu, &info->flush_pending) && + info->flush_cpu_ctxt_cb) + info->flush_cpu_ctxt_cb(); atomic64_set(&active_asid(info, cpu), asid); raw_spin_unlock_irqrestore(&info->lock, flags); @@ -427,6 +430,11 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm) post_ttbr_update_workaround(); } +static void asid_flush_cpu_ctxt(void) +{ + local_flush_tlb_all(); +} + static int asids_update_limit(void) { struct asid_info *info = &asid_info; @@ -499,6 +507,7 @@ static int asids_init(void) info->active = &active_asids; info->reserved = &reserved_asids; + info->flush_cpu_ctxt_cb = asid_flush_cpu_ctxt; /* * We cannot call set_reserved_asid_bits() here because CPU -- 2.17.1