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[124.44.145.191]) by smtp.gmail.com with ESMTPSA id b21sm255987pji.39.2021.04.14.14.02.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 14:02:52 -0700 (PDT) Date: Thu, 15 Apr 2021 06:02:49 +0900 From: Stafford Horne To: Peter Zijlstra Cc: Guo Ren , Christoph =?iso-8859-1?Q?M=FCllner?= , Palmer Dabbelt , Anup Patel , linux-riscv , Linux Kernel Mailing List , Guo Ren , Catalin Marinas , Will Deacon , Arnd Bergmann , jonas@southpole.se, stefan.kristiansson@saunalahti.fi Subject: Re: [RFC][PATCH] locking: Generic ticket-lock Message-ID: <20210414210249.GK3288043@lianli.shorne-pla.net> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 14, 2021 at 02:45:43PM +0200, Peter Zijlstra wrote: > On Wed, Apr 14, 2021 at 12:16:38PM +0200, Peter Zijlstra wrote: > > On Wed, Apr 14, 2021 at 11:05:24AM +0200, Peter Zijlstra wrote: > > > > > That made me look at the qspinlock code, and queued_spin_*lock() uses > > > atomic_try_cmpxchg_acquire(), which means any arch that uses qspinlock > > > and has RCpc atomics will give us massive pain. > > > > > > Current archs using qspinlock are: x86, arm64, power, sparc64, mips and > > > openrisc (WTF?!). > > > > > > Of those, x86 and sparc are TSO archs with SC atomics, arm64 has RCsc > > > atomics, power has RCtso atomics (and is the arch we all hate for having > > > RCtso locks). > > > > > > Now MIPS has all sorts of ill specified barriers, but last time looked > > > at it it didn't actually use any of that and stuck to using smp_mb(), so > > > it will have RCsc atomics. > > > > > > /me goes look at wth openrisc is.. doesn't even appear to have > > > asm/barrier.h :-/ Looking at wikipedia it also doesn't appear to > > > actually have hardware ... > > > > FWIW this is broken, anything SMP *MUST* define mb(), at the very least. > > As near as I can tell this should do. The arch spec only lists this one > instruction and the text makes it sound like a completion barrier. Yes, I will submit this patch. The l.msync instruction completes all load/store operations. The l.lwa/l.swa pair (used for xchg/cmpxchg) also implies l.msync. > --- > arch/openrisc/include/asm/barrier.h | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/openrisc/include/asm/barrier.h b/arch/openrisc/include/asm/barrier.h > new file mode 100644 > index 000000000000..7538294721be > --- /dev/null > +++ b/arch/openrisc/include/asm/barrier.h > @@ -0,0 +1,9 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_BARRIER_H > +#define __ASM_BARRIER_H > + > +#define mb() asm volatile ("l.msync" ::: "memory") > + > +#include > + > +#endif /* __ASM_BARRIER_H */